Blog Review: Sept. 10

Cadence’s Satish Kumar C explains Port-Based Routing, a feature in in CXL 3.0 and 3.1 that changes how CXL switches operate within a CXL fabric to enable the creation of much larger, more flexible, and more efficient topologies.

Siemens’ Bill Hargin demystifies copper foil thickness and weight measurements and why being precise has an impact on signal integrity and crosstalk simulations.

Synopsys’ Rob Kruger recommends eight best practices for chiplet-based designs, from smart system partitioning to treating security as a foundational element.

Arm’s Waheed Brown investigates how to scale LLM inference by distributing weights and computations across many machines.

Keysight’s Roberto Piacentini Filho suggests that global design platforms for semiconductor design data management can help in streamlining day-to-day chip design tasks to maximize productivity.

Ansys’ Caty Fairclough checks out how digital twins are being used in the military and defense industry to speed up development cycles and monitor systems after deployment.

And don’t miss the blogs featured in the latest Automotive, Security & Emerging Technologies and Test, Measurement & Analytics newsletters:

Technology strategy advisor Geoff Tate finds that robot exuberance is premature, and suggests application-specific machines are the near future, with humanoids after 2035.

Rambus’ Maxim Demchenko explains how different security protocols come together to protect valuable data.

Synopsys’ Gunnar Braun shows why traditional emulation-based techniques and tools fall short when it comes to modern automotive processors.

Siemens’ Shetha Nolke investigates proactive strategies for robust analog and sensor performance in automotive ICs.

Infineon’s Yufeng Pan explains how to ensure both Bluetooth hardware and software are operating correctly.

Keysight’s Marc Witteman focuses on ways to minimize the impact of cyberattacks on energy infrastructures.

Synaptics’ Neeta Shenoy looks at what happens when the sensor-driven, networked structure of IoT is combined with the decision-making power of edge AI.

Imagination’s Eleanor Brash compares the fillrate requirements of a specific GUI with the real-world performance of a GPU.

Cadence’s Reela Samuel weighs the impact of integrating all design domains into a coherent workflow.

Onto Innovation’s Damon Tsai, Woo Young Han, and Tim Kryman talk about how traditional bump technologies and hybrid bonding are advancing in parallel, each with unique strengths and limitations.

Modus Test’s Jesse Ko points out that the cost of false failures caused by the sockets is skyrocketing due to the extended test time of system-level testing.

PDF Solutions’ John Kibarian considers how AI, geopolitics, and the increased need for collaboration are reshaping the chip industry.

Advantest’s Roberto Colecchia suggests leveraging early data to guide everything from e-test to system-level validation.

Synopsys’ Yervant Zorian looks into how silicon health becomes much more complex for stacked dies with limited probe access.

proteanTecs’ Eyal Fayneh digs into the impact of in-chip telemetry on peak power, average power, and Di/Dt noise.

Nordson’s Anthony Buzzerio and Master Bond’s Venkat Nandivada and Rohit Ramnath discuss precise application of biocompatible adhesives to ensure long-term sensor reliability and performance.