Case Study: Production Yield And Throughput Improvement Using The Known Good Socket Analysis

The test sockets, which are crucial components that directly interface with semiconductor IC packages, have a profound impact on device testing performance. Pins with high CRES not only cause false failures in the test but also lower bin grading results, which in turn increase the manufacturing cost due to reduced production performance. The ever-increasing demand driven by high-performance computing is leading to a rise in the defect density of pins in a socket, especially with the increasing number of advanced package pin counts. The cost of false failures caused by the sockets for system-level testing (SLT) is skyrocketing due to the extended test time, often exceeding several hours per device while the manufacturing cost remains significant for lower to medium pin-count packages with high performance, due to its impact on the first-pass yield and retest rates, which is directly related to capacity issues. Our customers leverage a scientific data-driven problem-solving capability enabled by the high density and accuracy of the MPT, along with its graphical problem-solving tools.

Vicious cycles of yield issues over multiple product families

This particular customer experienced ongoing yield issues, resulting in low OEU and OEE, long cycle times, low throughput, and customer dissatisfaction. Signatures of the yield issues included multi-site yield variations, setup-to-setup and factory-to-factory yield variations, high pin replacement costs, low first-pass yield with a high retest rate.

Due to ineffective problem-solving techniques, typical labor-intensive remedies, such as pin cleaning and replacement, socket replacement, and load board cleaning and replacement, were applied without addressing the root cause, along with an automated laser socket cleaning tool.

This resulted in a vicious cycle of high manufacturing costs with the product families over several years.

Initial assessment by CRES measurement using the MPT

The initial assessment using the MPT quickly identified a significant shift in the CRES measurements of used pins with 23,000 insertions, which is significantly below the average performance of the pins.

Further analysis revealed the crown signature of poor CRES-performing pins, which were confirmed to be power and ground pins on the package.

DOE

A simple DOE with multiple CRES measurements at multiple insertion points was designed to identify the severity of degradation. The DOE revealed that the abnormal CRES degradation occurred only after 400 cycles of device testing.

SEM analysis

The SEM analysis of the pins with high CRES revealed a diffuse extra layer built up on the tips of the Power and Ground pins, caused by the lead from solder balls and the type of pin tip metal alloy, resulting from the high temperatures and currents induced during product testing. It explained why laser cleaning of the pins was ineffective, resulting in ongoing yield issues.

Recommendation

Based on the findings, the final recommendation was made to replace the existing pins with a new type of pins to prevent layer buildups and to use ModusTest KGS for socket validation and selection in the future.