Blog Review: Oct. 1

Synopsys’ Chun-Soo Kim and Hoseong Kim suggest making the entire design flow local layout effect-aware to identify and address issues early and ultimately improve PPA by avoiding overly pessimistic designs.

Siemens’ Kirk Fabbri explores the power distribution network, focusing on power plane capacitance and how it varies with the dynamic switching characteristics of the load and dielectric constant.

Cadence’s Shyam Sharma highlights what’s new in HBM4, from reduced I/O and DRAM core voltage to remapping options that support post-packaging repair of potential issues.

Arm’s Simon Tatham continues verifying the double-precision division function in a set of optimized assembly-language routines for basic floating-point arithmetic, uncovering and fixing a bug in the original code.

Keysight’s Carrie Browen lays out a five-level framework for software-defined vehicle maturity and how each stage in the evolution from mechanically controlled systems to fully integrated, cloud-native ecosystems builds upon the last in terms of architecture, capabilities, and business potential.

Ansys’ Laura Carter and Susan Coleman check out a startup developing modular electric vehicles for flexible public transit that can dynamically adapt transportation capacity based on demand.

SEMI’s Anshu Bahadur invites manufacturing engineers to a digital twin workshop that will feature reference architectures for scalable data platforms, integration patterns that support digital twin ecosystems, real-world use cases from fabs and OSATs applying AI/ML at scale, and best practices in managing governance and security across complex data pipelines.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Technology Editor Brian Bailey finds that nobody is clear on how AI will disrupt design workflows, highlighting the difficulty in making predictions.

ChipAgents’ Yuheng Tang and Kexun Zhang point out that AI has already begun enhancing RTL design workflows but its exploration in verification remains in early stages.

Arteris’ Andy Nightingale explains why emerging chiplet, memory, and interconnect technologies need layered, automated solutions to deliver predictable performance.

Siemens EDA’s John Ferguson presents a holistic approach that treats the 3D-IC stack as a coupled physical system helps overcome thermal, stress, and reliability challenges.

Cadence’s Vanessa Do talks about eliminating the constraints of traditional, fixed-memory architectures and the need for flexible memory expansion and memory sharing among devices.

Keysight’s Jenn Mullen looks at the expansion of quantum technology from research laboratories and university classrooms into our daily existence.