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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Blog Review: May 1
By Jesse Allen - 01 May, 2019 - Comments: 0

Synopsys' Melissa Kirschner questions whether a unified standard for safety-related code development will be enough to secure connected cars as MISRA and AUTOSAR merge C++ guidelines. In a podcast, Mentor's Brent Klingforth and John McMillan share questions and answers about rigid-flex PCB design, including the value of incorporating flexible circuits and the key challenges faced when doing ... » read more

Power/Performance Bits: April 30
By Jesse Allen - 30 Apr, 2019 - Comments: 0

Printed supercapacitors Researchers at Drexel University and Trinity College created ink for an inkjet printer from MXene, a highly conductive two-dimensional material, which could be used to print flexible energy storage components, such as supercapacitors, in any size or shape. The material shows promise as an ink thanks to its high conductivity and ability to apply easily to surfaces usi... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Apr, 2019 - Comments: 0

A new working group has been proposed by Accellera to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. “Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” said Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog a... » read more

Blog Review: April 24
By Jesse Allen - 24 Apr, 2019 - Comments: 0

Rambus' Steven Woo checks out changes in the hardware used for neural network training and the importance of co-design of hardware and software. Cadence's Meera Collier makes an argument for why vehicle sensors watching the driver could prevent some distraction and fatigue-related crashes. Synopsys' Dan Lyon and Garrett Sipple point to some best practices for how to deal with a changing t... » read more

Power/Performance Bits: April 23
By Jesse Allen - 23 Apr, 2019 - Comments: 0

Tiny spectrometer Engineers at the University of Wisconsin-Madison, Sandia National Laboratories, and Huazhong University of Science and Technology developed a miniature spectrometer small enough to integrate with the camera on a typical cellphone without sacrificing accuracy. This miniature sensor is CMOS compatible. "This is a compact, single-shot spectrometer that offers high resolution ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 19 Apr, 2019 - Comments: 0

Intel acquired vision and video FPGA IP company Omnitek. Founded in 1998, the Basingstoke, England-based company has produced FPGA IP cores for video processing including conversion and enhancement, creating arbitrary image warps on a real time video stream, connectivity, and deep learning and AI inferencing. Terms of the deal were not disclosed. Qualcomm and Apple have dropped all litigatio... » read more

Blog Review: April 17
By Jesse Allen - 17 Apr, 2019 - Comments: 0

In a video, Mentor's Colin Walls digs into power management in embedded software with a particular look at the Power Pyramid model. Synopsys' Taylor Armerding checks out the state of application security at this year's RSA and finds that while organizations are paying attention to security through training and dedicated teams, roadblocks still remain. Cadence's Paul McLellan considers how... » read more

Power/Performance Bits: April 16
By Jesse Allen - 16 Apr, 2019 - Comments: 0

Faster CNN training Researchers at North Carolina State University developed a technique that reduces training time for deep learning networks by more than 60% without sacrificing accuracy. Convolutional neural networks (CNN) divide images into blocks, which are then run through a series of computational filters. In training, this needs to be repeated for the thousands to millions of images... » read more

Week In Review: Design, Low Power
By Jesse Allen - 12 Apr, 2019 - Comments: 0

IP Flex Logix debuted its new InferX X1 edge inference co-processor, which incorporates the interconnect technology from its eFPGAs and its inference-optimized nnMAX clusters. The chip focuses on high throughput in edge applications with a single DRAM and is optimized for small batch sizes in edge applications where there is typically only one camera/sensor. InferX X1 will be available as chip... » read more

Blog Review: April 10
By Jesse Allen - 10 Apr, 2019 - Comments: 0

Arm's Paul Whatmough discusses the growing use of real-time computer vision on mobile devices and proposes transfer learning as a way to enable neural network workloads on resource-constrained hardware. Cadence's Anton Klotz highlights a collaboration with Imec and TU Eindhoven on cell-aware test that reduces defect simulation time by filtering out defects with equivalent fault effects. M... » read more

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