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Week In Review: Design, Low Power

Inferencing at the edge; RISC-V 64-bit embedded; power management IP.

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IP
Flex Logix debuted its new InferX X1 edge inference co-processor, which incorporates the interconnect technology from its eFPGAs and its inference-optimized nnMAX clusters. The chip focuses on high throughput in edge applications with a single DRAM and is optimized for small batch sizes in edge applications where there is typically only one camera/sensor. InferX X1 will be available as chips for edge devices and on half-height, half-length PCIe cards for edge servers and gateways. It is programmed using the nnMAX Compiler which takes Tensorflow Lite or ONNX models. The internal architecture of the inference engine is hidden from the user. It supports integer 8, 16 and bfloat 16 numerics with the ability to mix them across layers as well as Winograd transformation for integer 8 mode for common convolution operations.

Wave Computing uncorked its AI platform, TritonAI 64, that provides 8-to-32-bit integer-based support for high-performance AI inferencing at the edge. It also includes bfloat16 and 32-bit floating point-based support for edge training in the future. Features include a MIPS 64-bit SIMD engine that is integrated with Wave’s dataflow and tensor-based configurable technology. Additional features include access to MIPS IDE as well as a Linux-based TensorFlow programming environment.

SiFive launched its S2 Core IP series for power- and area-constrained high performance 64-bit embedded applications, providing an always-on low power CPU that can be combined with high-performance CPUs that switch on only when applications demand performance. The first IP in the line, S21, is based on the RV64IMAC ISA, includes 64-bit AXI Ports, machine and user mode with 4 region physical memory protection, and a 3-stage pipeline with simultaneous instruction and data access. The S2 Series will be available as a customizable Core IP Series as well as in the form of standard cores.

Vidatronic announced a series of integrated power management unit (PMU) IP cores optimized for integration with RF, wireless, and NB-IoT ASICs and SoCs. As well as integrating into an ASIC or SoC, the cores can be used separately in other applications. The series contains a dual-mode low dropout (LDO) voltage regulator with Vidatronic’s Power Quencher technology, a buck DC-DC converter, a low-power voltage reference, a high-accuracy bandgap reference, and a dual power switch. The IP is silicon-proven on TSMC’s 40nm process.

Events
DAC 2019: June 2-6 in Las Vegas, NV. The conference and exhibition includes a range of tracks, including last year’s addition of machine learning/AI. On the show floor, the Design Infrastructure Alley will return for a second year. Free registration is now open to attend the exhibits and keynotes, sponsored by Avatar Integrated Systems, ClioSoft and Truechip.

ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West.



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