Week In Review: Design, Low Power

Analog/mixed-signal plus UVM; PCIe 5.0 IP; security verification; TSMC certifications.


A new working group has been proposed by Accellera to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. “Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” said Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog and mixed-signal extensions to UVM and determine if a path to standardization is feasible. We encourage all interested companies to join our initial PWG meeting and provide input for standardization.” The first UVM-AMS Proposed Working Group meeting will be held Wednesday, May 22 at NXP Semiconductors, Schatzbogen 7, 81829 Munich, Germany. The meeting is planned from 10am to 4pm CEST and will cover presentations on industry best practices, discuss scope and requirements, and explore directions for standardization. Attendance is open to everyone, but registration is required.

Xilinx acquired Solarflare, a provider of high-performance, low latency networking solutions for markets including FinTech and cloud computing. Xilinx says it will enable combining its FPGA, MPSoC and ACAP solutions with Solarflare’s ultra-low latency network interface card (NIC) technology and Onload application acceleration software for new converged SmartNIC solutions. Xilinx was a strategic investor in Solarflare in 2017 and the companies have since been working together closely. Terms were not disclosed.

Mobiveil launched PCI Express 5.0 controller IP with end-to-end data path protection. The controller achieves the full PCIe 5.0 32Gbs bit rate per lane and is backward compatible with PCIe versions 4.0, 3.1, 2.0 and 1.1. Mobiveil offers all flavors of PCI Express including Root Complex, End Point, Dual mode and Switch configurations.

Arasan uncorked embedded Multi-Media Controller (eMMC) PHY IP on TSMC’s 7nm process. The PHY IP is integrated with Arasan eMMC 5.1 Host Controller IP and software. The eMMC 5.1 Specification from JEDEC improves HS400 speeds operating at 3.2Gbps through command queuing to make data transfers more efficient by offloading software overhead into the controller.

Tortuga Logic partnered with Synopsys on a security verification solution that identifies and prevents vulnerabilities in SoC designs by combining Synopsys’ ARC Processor IP and Tortuga Logic’s Radix-S security verification software. The collaboration provides a set of security threat models optimized for ARC processors that can verify whether a configuration or chip-level integration introduces any system security vulnerabilities.

Multiple tool vendors were certified for TSMC’s System-on-Integrated-Chips (TSMC-SoIC) 3D chip stacking technology, which expands upon the foundry’s 3D Wafer-on-Wafer (WoW) and Chip-on-Wafer (CoW) technologies by using a through silicon via (TSV) and chip-on-wafer bonding process for multi-die stacking on system-level integration. For more on this technology, check out TSMC’s chiplet strategy and Getting Down To Business On Chiplets.

ANSYS RedHawk and Totem products were certified for TSMC’s 5nm FinFET process technology. The tools provide extraction, power integrity and reliability, signal electromigration and thermal reliability analysis, and statistical EM budgeting analysis. ANSYS solutions were also certified for TSMC-SoIC.

Cadence’s digital, signoff and custom/analog tools have been certified for TSMC’s 5nm process Design Rule Manual (DRM) and SPICE v1.0, and Cadence IP has been enabled for the TSMC 5nm process with corresponding PDKs available for traditional and cloud-based environments. TSMC also certified Cadence’s design solutions for the new TSMC-SoIC.

Mentor had several tools in its Calibre nmPlatform and Analog FastSPICE Platform certified on TSMC’s 5nm FinFET process technology and made leakage checks available for full chip designs. Additionally, Mentor completed reference flow materials in support of TSMC-SoIC.

Synopsys digital and custom design platforms have been certified for TSMC’s latest Design Rule Manual (DRM) for its 5nm FinFET process technology. Synthesis and place-and-route tools offer extended support for advanced via-pillar implementation, multi-bit flip-flop (MBFF) banking/debanking, and leakage-power optimization. Additionally, Synopsys’ Design Platform has been certified for TSMC-SoIC.

Keysight’s PathWave Advanced Design System (ADS) and PathWave RFIC Design (GoldenGate) have been integrated with the latest interoperable PDK (iPDK) from Samsung for the 28FDS (28nm fully-depleted silicon-on-insulator) process technology.

Samsung’s System LSI Business renewed multiple licenses of Arteris IP’s FlexNoC Interconnect for use in multiple high-performance digital TV (DTV) processing chips utilizing Samsung’s latest process nodes. “This core interconnect technology is required to develop complex and highly optimized chips in a predictable, low-risk fashion,” cited Jaeyoul Lee, VP of Samsung Electronics.

LG Electronics signed a multi-year agreement with ANSYS for multiphysics simulation solutions, including  structures, fluids, and high-frequency electromagnetics suites. Sang Kook Kim, product development team task leader at LG, cited the deal as a “major milestone in the evolution and growth of our new product design and development processes.”

Desay SV adopted Synopsys’ Virtualizer virtual prototyping solution to accelerate software development for all of its advanced electronic automotive systems, including smart cabin and ADAS. Based in China, Desay SV is a Tier 1 supplier of in-vehicle infotainment systems, in-vehicle climatic controllers, digital instrument displays, and other automotive vehicle technologies.

Cadence reported financial results for the first quarter of 2019 with revenue of $577 million, up 11.6% from Q1 2018. On a GAAP basis, income per share for the quarter was $0.43, up 65.4% from $0.26 in Q1 last year. Non-GAAP income was $0.54 per share, up 35% from $0.40 for the same quarter last year. “We are raising our outlook for the year as technology trends like AI and 5G continue to drive strong design activity across all lines of our business,” said John Wall, senior vice president and CFO.

Rambus reported financial results for the first quarter of 2019 with revenue of $48.4 million, up 4.3% from Q1 2018. On a GAAP basis, there was a net loss per share of $0.24, a 27% change compared to a net loss of $0.33 per share for the same quarter last year. Non-GAAP loss per share was $0.08 for Q1 2019, 20% improved from a net loss per share of $0.10. In particular, the company noted that DDR4 server DIMM chipset revenue was up nearly 40% year-over-year.

Accellera UVM-AMS PWG Kickoff: May 22 in Munich, Germany. A meeting to assess industry interest in standardizing analog/mixed-signal extensions for UVM. Open to all, but registration is required.

ESD Alliance CEO Outlook: May 23 6:00 p.m. to 8:300 p.m. in Milpitas, CA. This year’s panelists extend across the semiconductor supply chain: John Chong, vice president of product and business development for Kionix, Jack Harding, president and CEO of eSilicon, John Kibarian, PDF Solutions’ president and CEO, and Wally Rhines, CEO emeritus of Mentor, a Siemens Business. Attendance is free, but registration is required.

DAC 2019: June 2-6 in Las Vegas, NV. The conference and exhibition includes a range of tracks, including last year’s addition of machine learning/AI. On the show floor, the Design Infrastructure Alley will return for a second year. Free registration is now open to attend the exhibits and keynotes, sponsored by Avatar Integrated Systems, ClioSoft and Truechip.

ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West.

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