tag: DDR4

Interference Risks In Processing-Using-DRAM (U. of Tokyo, ETH Zurich, CISPA, Riken)
By Technical Paper Link - 22 Jun, 2026 - Comments: 0

Researchers from The University of Tokyo, ETH Zurich, CISPA, and RIKEN published a technical paper titled “PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems.” Abstract excerpt: “We reveal PuDGhost, an interference phenomenon where a PuD operation in a given column produces erron... » read more

In-DRAM TRNG Using Simultaneous Multiple-Row Activation (ETH Zurich, CISPA)
By Technical Paper Link - 31 Oct, 2025 - Comments: 0

A new technical paper titled "In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips" was published by researchers at ETH Zürich and CISPA. Abstract "In this work, we experimentally demonstrate that it is possible to generate true random numbers at high throughput and low latency in commercial off-the-shelf (COTS) DRAM chi... » read more

Expanding Server Memory Capabilities With Multiplexed Rank DIMM (MRDIMM) Technology
By Rambus - 16 Jul, 2025 - Comments: 0

The scaling of computational power within a single, packaged semiconductor component continues to rise following a Moore’s law type curve enabling new and more capable applications including machine learning (ML), generative artificial intelligence (AI), and training and deployment of large language models (LLM). On-demand lifestyle applications like language translation, direction finding, a... » read more

Chiplet Tradeoffs And Limitations
By Ann Mutschler - 10 Apr, 2025 - Comments: 0

The semiconductor industry is buzzing with the benefits of chiplets, including faster time to market, better performance, and lower power, but finding the correct balance between customization and standardization is proving to be more difficult than initially thought. For a commercial chiplet marketplace to really take off, it requires a much deeper understanding of how chiplets behave indiv... » read more

Experimental Characterization Results and State-of-the-Art Device-Level Studies of DRAM Read Disturbance
By Technical Paper Link - 25 Mar, 2025 - Comments: 1

A new technical paper titled "Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies" was published by researchers at ETH Zurich. Abstract "Modern DRAM is vulnerable to read disturbance (e.g., RowHammer and RowPress) that significantly undermines the robust operation of the system. Repeatedly opening and closing a DRAM ro... » read more

Temporal Variation in DRAM Read Disturbance in DDR4 and HBM2 (ETH Zurich, Rutgers)
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A new technical paper titled "Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance" was published by researchers at ETH Zurich and Rutgers University. Abstract "Modern DRAM chips are subject to read disturbance errors. State-of-the-art read disturbance mitigations rely on accurate and exhaustive characterization of the read disturbance threshold... » read more

Memory System Benchmarking, Simulation, And Application Profiling Via A Memory Stress Framework
By Technical Paper Link - 22 May, 2024 - Comments: 0

A technical paper titled “A Mess of Memory System Benchmarking, Simulation and Application Profiling” was published by researchers at Barcelona Supercomputing Center, Unversitat Politecnica de Catalunya, and Micron Technology (Italy). Abstract: "The Memory stress (Mess) framework provides a unified view of the memory system benchmarking, simulation and application profiling. The Mess benc... » read more

Rowhammer Exploitation On AMD Platforms, DDR4 DDR5 (ETH Zurich)
By Technical Paper Link - 03 Apr, 2024 - Comments: 0

A new technical paper titled "ZenHammer: Rowhammer Attacks on AMD Zen-based Platforms" was published by researchers at ETH Zurich. The work will be presented at USENIX Security Symposium in August 2024. Abstract: "AMD has gained a significant market share in recent years with the introduction of the Zen microarchitecture. While there are many recent Rowhammer attacks launched from Intel CPU... » read more

DRAM Chip Characterization Study of Spatial Variation of Read Disturbance and Future Solutions (ETH Zurich)
By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A new technical paper titled "Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions" was published by researchers at ETH Zurich. Abstract: "Read disturbance in modern DRAM chips is a widespread phenomenon and is reliably used for breaking memory isolation, a fundamental building block for building robust systems. Row... » read more

How To Stop Row Hammer Attacks
By Ed Sperling - 30 Jan, 2024 - Comments: 0

Row hammer is a well-publicized target for cyberattacks on DRAM, and there have been attempts to stop these attacks in DDR4 and DDR5, but with mixed results. The problem is that as density increases, distance decreases, making it more likely that flipped bit cell in one row can disturb a bit cell in another, and that bits flipped across an entire row can flip another row. Steven Woo, fellow and... » read more

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