Getting Down To Business On Chiplets

Consortiums seek ways to ensure interoperability of hardened IP as way of cutting costs, time-to-market, but it’s not going to be easy.


Government agencies, industry groups and individual companies are beginning to rally around various chiplet models, setting the stage for complex chips that are quicker and cheaper to build using standardized interfaces and components.

The idea of putting together different modules like LEGOs has been talked about for the better part of a decade. So far, only Marvell has used this concept commercially, and that was exclusively for its own chips based on what it calls a modular chip (MoChi) architecture. Since then, three separate initiatives have been started involving DARPA; IEEE’s International Roadmap For Devices and Systems in conjunction with SEMI; and a group of companies including Netronome, Achronix, Kandou Bus, GlobalFoundries, NXP, Sarcina Technology, and SiFive. There also is work being done in Europe by Leti and Fraunhofer, among others.

“Next year you’ll be hearing a lot more about chiplets,” said Yaniv Kopelman, networking CTO and senior director at Marvell. “Chiplets are a good solution to the death of Moore’s Law. We implemented this three years ago on a switch, and we have been re-using technology across our product line internally.”

Marvell introduced its MoChi architecture, which is based on Kandou’s interconnect fabric, three years ago. Since then, momentum has begun building for other companies to get involved, spurred by the rising cost of device scaling and an almost constant state of flux in AI algorithms and new markets such as automotive chips and 5G.

Fig. 1: MoChi example in a smartphone. Source: Marvell

“The rate of change has increased,” said Naveed Sherwani, CEO of SiFive. “So now we have fast-changing algorithms, and you want to use an ASIC or something close to an ASIC versus FPGA speed, power and cost. But we’re also seeing, particularly with AI, that Moore’s Law has come to a grinding halt because shrinking is not helping. If there is no next node, a chiplet approach becomes more viable.”

Sherwani said this also could lower the barrier to entry for companies developing chips, helping to draw in new talent and younger engineers as the semiconductor industry becomes more affordable and dynamic.

There is much support for that approach, particularly among startups and investors.

“Chiplets will increase the rate of sales, and there will be more innovation” said Amin Shokrollahi, CEO of Kandou Bus. “And this will accelerate innovation because you are designing only one part. This has been the driver among IP houses and the IP business in general. You grab one IP from here and another from there. But where this has run into problems is putting these IPs together. That part is tough.”

Providing a framework and some standardization can help, and it can significantly decrease the cost and speed of designs.

“We have to fundamentally decrease the cost of innovation,” he said. “That means we need to figure out how to get to market in three months and understand why we make the same mistakes. The burden of integration has been roughly the same over the past 40 years. We need to be able to do a project with 5 to 10 people, not 200 people, and it needs to be done quickly.”

There is still much work ahead to make that happen, and the concept still has yet to be proven commercially beyond a single company. Being able to add enough consistency and flexibility across a global supply chain in a cost-effective way is a significant challenge, but the implications of getting this right are profound.

“The real value in all of this is a catalog of chiplets so that you can track where a chip has gone and what issues people have experienced working with that IP,” said Ranjit Adhikary, vice president of marketing at ClioSoft. “What you really want is a model like Amazon, where you have specs and reviews for each IP, whether that’s hard or soft IP. That’s very important. That has to be complemented by security, so some groups have access to certain IPs and not others. And all of it needs to be translated into a data management system where you understand the liabilities and you can keep track of IPs and how they are being used.”

Challenges ahead
Creating an infrastructure with multiple companies developing hard IP isn’t trivial. And it becomes harder as chips are developed by multiple companies in multiple regions. Sometimes there are language issues, and characterization for reliability, security, and electrostatic/proximity effects may need to be more precise for some applications than others. This is particularly true for safety-critical applications, as well as for combinations of chips involving components developed at advanced process nodes.

“Every time you add a new device, the complexity increases by two to three times,” said Gert Jorgensen, vice president of sales and marketing for DELTA Microelectronics. “We’ve done two-chip packages with 180, 40 and 28nm, but all of those were custom-designed chips. That makes it easier because they were designed to fit together. If you make everything more standardized, they are not tailored to each other.”

There are other issues, as well. “When you’re dealing with more than one vendor, there are problems like getting delivery on time,” said Jorgensen. “So you may have 25 wafers from each company, but you only get 23 good ones from one vendor. Or sometimes the wafers are contaminated and not easy to bond.”

Marvell’s Kopelman said one of the big problems Marvell encountered was the interface between chips. For cost reasons, the interface needed to run over an organic substrate, rather than using an interposer. A second problem involved partitioning.

“When you architect chiplets, sometimes you are dividing IP in the middle,” he said. “The challenge is where to cut and how to develop the architecture that allows for that. With a switch or a CPU, the main concern is latency of components. Another problem is getting all of this into production. It’s easy to build IP that works in a demo, but that’s a long way to production-worthy IP. It needs to pass tests for ESD, hot, cold, and varying processes. That’s a lot of work and it takes time.”

Speeding up packaging
While much of the attention involving chiplets focuses on time to market and customization, they also can be used with conventional packaging such as fan-outs. One of the big challenges there is die placement.

“Chiplets conceptually are a very good way to build fan-outs with something like an EMIB (Intel’s embedded multi-die interconnect bridge),” said Bill Chen, fellow and senior technical advisor at ASE. “But this isn’t easy. With fan-outs and other technologies you need to place the die precisely on the substrate and then use a redistribution layer. With the fan-out process, though, a die will move.”

While fan-outs already are in volume production, notably in smart phones based on TSMC‘s InFO architecture, the broader application of this packaging approach is just beginning.

“There are very few implementations of multi-die yet,” said Chen. “Designs need to catch up and cost needs to catch up. There are a number of different ideas being tried out. ASE has tried out two die for chip last and two for chip first, and both work.”

The next step is adding repeatability with confidence, and that may require a variety of new approaches. Brewer Science is working on one such approach, using a thin film in a mold compound that works like a stencil. The approach could significantly reduce die movement issues.

“This is not an interposer,” said Rama Puligadda, Brewer’s executive director of advanced technologies. “It’s a replacement for EMC (epoxy mold compound). You pre-form a stencil where you want to make cavities in silicon.”

She noted that also helps with issues such as warpage, which is a growing problem with EMC. A chiplet approach is more modular, which reduces mechanical stress on the various parts.

Fig. 2: Laminated polymetric die-stencil fill concept. Source: Brewer Science.

Who’s doing what
DARPA’s CHIPS (Common Heterogeneous Integration and IP Reuse Strategies) program has won the backing of Boeing, Lockheed, Northrop Grumman, Intel, Micron, Cadence, Synopsys and others for commercial and mil/aero applications. SEMI and IEEE likewise are promoting a common road map for faster integration, and Mentor, a Siemens Business, has established a packaging flow that can help in this regard.

But moving this to a mainstream commercial level has a long way to go. ““So far, there are no defined communication protocols for die-to-die communication,”” said Steve Mensor, vice president of marketing at Achronix. ““Protocols used for standalone device for chip-to-chip communication can be used, but these have large latency overhead and would be suboptimal for the package integrated solution. The chiplet use case will expand quickly once there are defined standards available.””

Mensor said the vision is better interoperability rather than better characterization. ““The end goal is creating standard products that can reliably interoperate with any other chiplet in a package integrated solution. This will require standards and interoperability certification methodologies. Otherwise, each packaged solution will be a significant engineering effort to build the custom solution.””

That requires domain knowledge, which changes the game on multiple levels. The driving concept behind this is what amounts to mass customization, an approach that third-party IP was supposed to facilitate. What has been missing is a way to put those pieces together more predictably.

“You need domain knowledge, and you need to keep the application of that domain in mind because for AI, networking and security you are dealing with domain-specific languages,” said Sujal Das, chief marketing and strategy officer at Netronome Systems. “That’s the way to get more value from performance per watt. You want a maximum amount of choice in terms of differentiation. Today, when you source SerDes IP from different vendors, you are forced into a certain process geometry. If you want to move to 5G PAM-4, you need 7nm, so you’re forced to move everything. But other IP should be able to stay at the node that is best, and to make that work you need an open way of connecting these things. Intel’s EMIB is overkill for this. You want to enable connection in a flexible way.”

Das said that requires both synchronous and asynchronous approaches, as well as a common connectivity fabric. Netronome has opened up its switch fabric to facilitate this.

“The first step will be to create a white paper on a spec,” he said. “Then, we will release spects and beef them up. We expect to have a prototype in Q1 or Q2 of next year.”

From there, tools and methodologies will need to be developed to make all of this work. While smaller chips have better yield than larger chips, there are many things that can go wrong as these chips are packaged together. One bad chiplet can kill an entire package. In addition, chips or modules can be damaged in packaging, test or even in transit, and the cost of that damage is higher if there are multiple chips involved

“When the die size is bigger, yield decreases,” said S.W. Yoon, director of group technology strategy for the JCET Group. “We’ve seen this in fan-outs. As the size gets bigger, to 10 x 10 or 20 x 20, the yield is lower.”

Yoon said the emphasis now is on thinner packages and interconnections of 2µ or less, particularly in fan-outs. That means chiplets used in those types of devices will need to be characterized for the same kinds of density and possible interactions as chips that are custom-designed today, and tools will need to account for different IP capabilities and limitations.

“Tooling is a major thing that’s needed,” said Kandou’s Shokrollahi. “We have some tools in-house that were developed with Marvell. But there is still quite a bit that is lacking.”

Tools provide more consistency in configuring these devices. They also reduce the number of errors that can creep into designs, particularly when complexity exceeds the capability of the human brain to map all of the possible interactions and electrical implications of floorplanning in multiple dimensions.

That tooling starts on the planning side with EDA, but it continues into the inspection and test phases of manufacturing. In some cases the tools drive methodologies, and in some cases the reverse is true. But once that basis is established, it provides leeway to refine the process, cut costs, and to experiment with new possibilities such as inter-die silicon photonics.

While photonics has been on the horizon for some time, it has mainly been used between various types of servers and storage in large data centers. Putting it into a package would have a significant impact on performance, latency and heat-related effects. But how quicky this can be introduced on a commercial scale at a competitive price point is unknown at this point.

That said, there is significant momentum toward chiplets, and numerous discussions involving chiplets at technical conferences over the past year often include a mention of photonics as a future direction.

Commercially available chiplets are still at least a few years away. They have been shown to work in limited applications, and it’s quite possible a large part of the chip industry will head in this direction over time. But there are still issues to iron out, and it will require the work of many companies rather than just a few.

“We’re not making chiplets today, but we have looked at it,” said Jack Harding, president and CEO of eSilicon. “My personal view is that it’s an inevitable part of module development and, more broadly, chip development.”

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