Getting Serious About Chiplets

Issues involving known good die and test still remain, but this approach is getting a lot of interest.


Demand for increasingly complex computation, more features, lower power, and shorter lifecycles are prompting chipmakers to examine how standardized hard IP can be used to quickly assemble systems for specific applications.

The idea of using chiplets, with or without a package, has been circulating for at least a half-dozen years, and they can trace their origin back to IBM’s packaging scheme in the 1960s. It is now picking up steam, both commercially and for military purposes, as the need for low-cost semi-customized solutions spreads across a number of new market opportunities.

As with any new approach, though, there are technical and ecosystem issues that need to be ironed out. For chiplets, there are several issues. One is how to verify and test the various pieces, both individually and in the context of other chiplets. A second is who takes responsibility for the chiplets once they are manufactured and handed off to the integrator or packaging house, which is the familiar known good die issue. And third, the chiplet approach raises a variety of competitive issues that could well upset the status quo.

“If you look at where things are going, soon it will be down to four or five companies that can even do large scale 7nm or 5nm design with any expectation of getting it to work and making money,” said Ty Garibay, CTO of ArterisIP. “Not only is it hard to justify the cost of these advanced nodes, it’s also hard to find people that can do it. It’s a difficult task, and you have a limited number of talented designers that are going to be able do it for you. These big companies may consider building the active substrate at 7nm or 5nm if yields are good enough, and then using chiplets to implement high speed IO or other special functions. However, if a startup can create a 100X improvement and still have the performance advantage because their smart, whether the function is implemented in 22nm and gives up 30% or 40% performance probably doesn’t matter. They are still ahead. Maybe then they can get enough money to get into the game at the more advanced nodes with that first product. But you can get into the game with a far smaller investment up front.”

Chiplets potentially can provide that lower cost of entry, particularly at the most advanced nodes where currently there are not a lot of players due to the cost of developing chips. That has garnered a lot of attention lately as these end markets gain footing and new ones spring up.

Fig. 1: Pros and cons for SoCs, chiplets and traditional system design. Source: Semico Research

Speed bumps
While a possible ticket to success, there are a variety of considerations system architects and design teams need to keep in mind. One is that system-level test of chiplets must be accounted for in the architecture of the system.

“The interesting thing with chiplets that’s a bit different from a monolithic device is that you’re packaging up multiple chiplets typically with one ASIC,” said Hugh Durdan, vice president, strategy and products at eSilicon. “What you get into with chiplets is that, let’s say every chiplet has 98% yield, which sounds like a high number. But all of a sudden, you put 10 of them sitting next to the ASIC, and the cumulative yield on those 10 chiplets is .98 to the 10th power. That is dramatically lower than 98%, so the conclusion is that 98% isn’t good enough. What you really need, if you are the purchaser of a chiplet, is that for that chiplet to be a known good die, which is virtually 100% yield. And you need it to be fully tested, qualified, and you need to be able to rely on it so that you’re not going to take a cumulative yield loss when you put lots of these things all in one package.”

This is an extra demand that’s placed on the supplier of the chiplet, in addition to what typically is required for a semiconductor device, he noted. “If you’re the user who’s integrating those chiplets with an ASIC, then what you have to be worried about first is that what would normally be the I/O interfaces going out of the package to the external world from the ASIC are now replaced with interfaces that go between the ASIC and the chiplets. This means the number of signals used for the ASIC to communicate to the outside world coming out of the package is greatly reduced. By itself that can present problems for testability of the ASIC. One of the ways that’s addressed is by having people actually bring their scan chains and test interfaces not directly out of the package from the ASIC, because there aren’t enough I/Os, but instead going through the chiplet, and using the chiplet connection to the outside world for the test interface. This is another design consideration for the chiplet supplier. They have to be aware of these types of things when they design their chiplets.”

Then, the chiplet and the interface between the ASIC and chiplet must be tested, which is another area of consideration when you’re designing the whole system, Durdan said. “If the chiplet is a SerDes and you can put it in loopback mode, you have to be able to have access from the ASIC to give commands to the chiplet to put the SerDes in the loopback mode and not exercise the test, then make sure that it ran successfully, and so on. You have to be able to do that after it’s all packaged up because these wires that go between the chiplet and the ASIC can’t be brought outside of the chip. So you have to test both the integrity of the chiplet itself, but then also the connection between the ASIC and the chiplet. It has to be testable inside the package.”

Anil Bhalla, senior manager, marketing and sales, for Astronics Test Systems, agreed. “Chiplets offer the promise of enabling the integration of functional IP at a chip or chiplet level, while at the same time enabling applications to take advantage of lower or advanced nodes. The challenge is to develop a usable interface standard, and as that is adopted, the ability to integrate IP from suppliers of choice is expected to accelerate.”

From a test perspective, Astronics sees the testing of chiplets to be similar to the increasing trend toward heterogeneous integration with devices such as SiPs and multi-core SoCs.

“Expectations are that chiplets will operate as a solution, not a collection of individual IPs. We see system-level test being a valuable part of a test strategy for chiplets,” Bhalla said. “At the same time, similar to SiPs, there is a challenge when one combines IP from different vendors. Even if you could guarantee 100% incoming yield from all of your IP suppliers, combining the IP into a common device will not guarantee 100% yield. Trying to write test patterns for standard ATE is extremely challenging, both from a designer’s perspective to have the time to develop the patterns, and from a test engineer’s perspective to be able to afford the production test time to run all the patterns. System-level test offers some exciting tools to test the chiplet as a solution — along with the software (drivers, boot up routines), as well as the associated hardware.”

Again, because chiplets present the same test challenges as 2.5D packaging, ensuring they are from known good die, and ensuring connections between the chiplets on the substrate/board are properly tested, is essential.

“In the traditional single die IC manufacturing process, most of the defective die are eliminated during wafer test,” explained Steve Pateras, product marketing director at Mentor, a Siemens Business. “However, wafer testing is inherently limited by the number of probes that can be used to apply stimuli and measure responses of the die on a wafer. Limitations in access to power and ground rails can also limit the ability to apply tests at the full target speed of the device. Because of the cost of overcoming these inherent wafer test limitations, the historic approach has been to allow some test escapes at the wafer level and to catch these during package test.”

In the chiplet package flow, the escape rate at wafer test has a much larger impact on final packaged (board) yield, he said. “This is because a defective die, when packaged with good die, will result in a failure of the entire package (board). This combinational effect means the impact of wafer escapes is magnified exponentially in the final product, adversely affecting package yield.”

In addition, the cost of defects after packaging is higher because there is more value bound up in a chiplet package. Because of these two reinforcing effects there is a higher KGD test quality requirement at wafer test for chiplets. This may be achieved by test patterns with higher fault coverage and possibly by the introduction of additional fault models to test for defects that are normally ignored at wafer test.

Testing the interconnect between the chiplets on the substrate can be done in two ways, Pateras explained. “Traditional boundary scan techniques used for testing between packaged chips on boards or modules can be used if the overhead of adding boundary scan chains to the chiplets is possible. If adding boundary scan chains to all the chiplets is not physically or economically possible, the chiplets can be treated essentially as IP cores, and hierarchical test techniques traditionally used for cores within large SoCs can be used to test the interconnect instead. What’s more, hierarchical ATPG allows the test patterns used to test the chiplets during wafer sort to be re-used almost as is at the package level for testing any internal chiplet defects that may have been introduced during the packaging process.”

On the verification side, chiplets can be viewed as the next element along the axis of reuse in the design flow.

“At the most abstract are behavioral models that have to go through high-level synthesis, then RTL models that go through logic synthesis and layout to hard IP that has been fully laid out and now chiplets, prefabricated pieces of IP,” noted Adnan Hamid, CEO of Breker Verification Systems.

The verification side of this has not moved in the same way, which is why the time and cost of verification has been increasing.

There is a growing awareness of Portable Stimulus playing a role here because the models can be assembled in the same way as IP blocks, unlike UVM models that cannot. A PSS model is a complete specification of what a block is supposed to be able to do and results it should provide, and can also carry information about the testing performed on it, Hamid said.

“When assembling these at the system level, it thus becomes easy to see if the design will activate paths through the chiplet that have never been tested before,” Hamid said. “Testcases also will be created that verify the interactions between the chiplets. Portable stimulus testcases can either be run on abstract models of the chiplets or on the actual devices themselves, perhaps integrated through some type of package breadboarding.”

Other issues
Those are just the obvious issues, too. Other problems can come up, depending upon which path companies choose.

“There are solutions with interposers or without,” said Raymond Nijssen, vice president of systems engineering at Achronix. “You also have to think about data rates, because some solutions require very high data rates, and you also have to look at the reason why you’re doing chiplets in the first place, because you can’t afford to have that many balls on the package.”

He said that if it all works as planned, then chiplets can solve many problems in design. But it is hardly a panacea for all applications.

“You have to decide up front how much memory to pair with the CPU, and that’s difficult to change later on,” Nijssen said. “At the PCB level, this is modular, so you can change out one memory for another. With chiplets, you cannot create an inventory of package parts with memory. You can’t add a memory stack in at the time of the packaging. And inventory management here is not trivial. This is one of the issues DARPA is facing with chiplets. At the time of packaging, they have to decide what goes in there and make sure all of the products will be available for the entire product lifetime. If there is an end of life for a chiplet, can they fall back on something else. Or if a company gets acquired and you’ve built a product based on the presence of a chiplet, what happens?”

Complicating all of these issues are smaller process geometries, Astronics’ Bhalla pointed out. “The complexity of lower process geometries intensifies the complexity of testing chiplets. We expect to see a similar paradigm shift in test strategies as we currently see with devices moving to lower nodes. Often test strategies that worked at the higher nodes have to be supplemented with new test methodologies. Adding a system-level test strategy can help get closer to a 100% test coverage as it supplements the testing done with structural and functional test strategies.”

Chiplets continue to be an enticing possibility for companies. Marvell’s MoChi architecture, which is based on internally developed components, is a first step toward this kind of plug-and-play approach. But expanding this to include an entire ecosystem of IP providers adds some new challenges to this scheme.

While most of these issues can be solved, it’s not as simple as putting together different sized LEGO blocks and assuming everything will work together. There are a broad range of challenges and considerations to contend with, as well as a number of advantages that make this an increasingly popular idea for certain markets.

—Ed Sperling contributed to this report.

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