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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Research Bits: May 7
By Jesse Allen - 07 May, 2024 - Comments: 0

High-temperature memory Researchers from the University of Pennsylvania and Air Force Research Laboratory demonstrated memory technology capable of enduring temperatures as high as 600° Celsius for more than 60 hours while retaining stability and reliability. The non-volatile memory device consists of a metal–insulator–metal structure, incorporating nickel and platinum electrodes with a 4... » read more

Blog Review: May 1
By Jesse Allen - 01 May, 2024 - Comments: 0

Cadence's Vatsal Patel stresses the importance of having testing and training capabilities for high-bandwidth memory to prevent the entire SoC from becoming useless and points to key HBM DRAM test instructions through IEEE 1500. In a podcast, Siemens' Stephen V. Chavez chats with Anaya Vardya of American Standard Circuits about the growing significance of high density interconnect and Ultra ... » read more

Research Bits: April 30
By Jesse Allen - 30 Apr, 2024 - Comments: 0

Sound waves in optical neural networks Researchers from the Max Planck Institute for the Science of Light and Massachusetts Institute of Technology found a way to build reconfigurable recurrent operators based on sound waves for photonic machine learning. They used light to create temporary acoustic waves in an optical fiber, which manipulate subsequent computational steps of an optical rec... » read more

Blog Review: April 24
By Jesse Allen - 24 Apr, 2024 - Comments: 0

Cadence's Vatsal Patel notes the factors that make high-bandwidth memory ideal for AI, such as improved bandwidth and area from vertical stacking and power reduction features like data bus inversion. Synopsys' Rob van Blommestein points to early power network analysis as a way to ensure that enough power is delivered to each transistor to mitigate potential power-related issues within the ch... » read more

Research Bits: April 23
By Jesse Allen - 23 Apr, 2024 - Comments: 0

Probabilistic computer prototype Researchers at Tohoku University and the University of California Santa Barbara created a prototype of a heterogeneous probabilistic computer that combines a CMOS circuit with a limited number of stochastic nanomagnets. It aims to improve the execution of probabilistic algorithms used to solve problems where uncertainty is inherent or where an exact solution... » read more

Blog Review: April 17
By Jesse Allen - 17 Apr, 2024 - Comments: 0

Siemens' Sumit Vishwakarma highlights the importance of crystal oscillators to the proper functioning of many semiconductor devices and applications, from clock signals to transmission and reception of radio waves. Cadence's Jay Domadia introduces some of the new features in GDDR7, such as a semi-independent row and column command address bus and two modes of data signaling, enabling PAM3 fo... » read more

Research Bits: April 16
By Jesse Allen - 16 Apr, 2024 - Comments: 0

Tunable thermal conductivity in memristors Researchers from the Center for Research in Biological Chemistry and Molecular Materials (CiQUS) and Forschungszentrum Juelich discovered that oxide-based memristive devices can demonstrate tunable thermal conductivity. Alongside the memristor's electrical resistive switching, a thermal resistive switching effect also occurs at the metal-oxide inte... » read more

Startup Funding: March 2024
By Jesse Allen - 10 Apr, 2024 - Comments: 0

The challenge of moving data from place to place is increasingly a key concern for chip and system designers, and investors are taking note. Numerous startups developing interconnect technologies received significant backing in March, with approaches spanning chiplet-enabling PHYs, photonic fabrics for disaggregated compute and memory, and telecom transceiver modules. Several new startups la... » read more

Blog Review: April 10
By Jesse Allen - 10 Apr, 2024 - Comments: 0

Cadence's Shyam Sharma looks at the evolution of the LPDDR standard and finds that LPDDR5X is opening new specialized markets for low-power DRAMs beyond the traditional areas of mobile, IoT, and automotive. Siemens' Hossam Sarhan and Dusan Petranovic find that new physical verification approaches are needed to ensure the performance and reliability of superconducting ICs and introduce a hybr... » read more

Research Bits: April 8
By Jesse Allen - 08 Apr, 2024 - Comments: 0

Annealing processor Researchers from the Tokyo University of Science designed a scalable, fully-coupled annealing processor with 4096 spins on a single board with 36 CMOS chips, with parallelized capabilities for accelerated solving of combinatorial optimization problems. "We want to achieve advanced information processing directly at the edge, rather than in the cloud, or performing prepro... » read more

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