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Laura Peters

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Laura Peters is senior executive editor for manufacturing and test at Semiconductor Engineering.

Author's Latest Posts

Enabling Test Strategies For 2.5D, 3D Stacked ICs
By Laura Peters - 08 Sep, 2022 - Comments: 0

Improved testability, coupled with more tests at more insertion points, are emerging as key strategies for creating reliable, heterogeneous 2.5D and 3D designs with sufficient yield.  Many changes need to fall into place to make side-by-side 2.5D and 3D stacking approaches cost-effective, particularly for companies looking to integrate chiplets from different vendors. Today, nearly all of t... » read more

MicroLEDs Move Toward Commercialization
By Laura Peters - 29 Aug, 2022 - Comments: 1

The market for MicroLED displays is heating up, fueled by a raft of innovations in design and manufacturing that can increase yield and reduce prices, making them competitive with LCD and OLED devices. MicroLED displays are brighter and higher contrast than their predecessors, and they are more efficient. Functional prototypes have been developed for watches, AR glasses, TVs, signage, and au... » read more

How Overlay Keeps Pace With EUV Patterning
By Laura Peters - 09 Aug, 2022 - Comments: 1

Overlay metrology tools improve accuracy while delivering acceptable throughput, addressing competing requirements in increasingly complex devices. In a race that never ends, on-product overlay tolerances for leading-edge devices are shrinking rapidly. They are in the single-digit nanometer range for the 3nm generation (22nm metal pitch) devices. New overlay targets, machine learning, and im... » read more

Hybrid Bonding Moves Into The Fast Lane
By Laura Peters - 21 Jul, 2022 - Comments: 1

The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

Improving Yield With Machine Learning
By Laura Peters - 12 Jul, 2022 - Comments: 0

Machine learning is becoming increasingly valuable in semiconductor manufacturing, where it is being used to improve yield and throughput. This is especially important in process control, where data sets are noisy. Neural networks can identify patterns that exceed human capability, or perform classification faster. Consequently, they are being deployed across a variety of manufacturing proce... » read more

Ways To Address The Materials Crunch
By Laura Peters - 16 Jun, 2022 - Comments: 0

Stellar growth over the last two years and the seemingly insatiable demand for chips, at least through 2025, is sparking massive investment by chip firms — as much as $500B over the next five years. But without significant boosts in raw materials, parts for tools, and silicon to fuel facilities, such numbers are unlikely to be met. Materials are the Achilles heel to the rapidly expanding c... » read more

Shortages Spark Novel Component Lifecycle Solutions
By Laura Peters - 19 May, 2022 - Comments: 0

The semiconductor industry’s supply chain problems are prompting some innovative solutions and workarounds, and while they don't solve all problems, they are improving efficiency and extending equipment lifetimes. The shortages, which affect everything from the chips used in automotive, IoT, and consumer ICs to the equipment used to manufacture and test them — span global supply lines. T... » read more

How AI/ML Improves Fab Operations
By Laura Peters - 10 May, 2022 - Comments: 0

Chip shortages are forcing fabs and OSATs to maximize capacity and assess how much benefit AI and machine learning can provide. This is particularly important in light of the growth projections by market analysts. The chip manufacturing industry is expected to double in size over the next five years, and collective improvements in factories, AI databases, and tools will be essential for doub... » read more

Strategies For Faster Yield Ramps On 5nm Chips
By Laura Peters - 12 Apr, 2022 - Comments: 0

Leading chipmakers TSMC and Samsung are producing 5nm devices in high volume production and TSMC is forging ahead with plans for first 3nm silicon by year end. But to meet such aggressive targets, engineers must identify defects and ramp yield faster than before. Getting a handle on EUV stochastic defects — non-repeating patterning defects such as microbridges, broken lines, or missing con... » read more

Extending Copper Interconnects To 2nm
By Laura Peters - 17 Mar, 2022 - Comments: 0

Transistor scaling is reaching a tipping point at 3nm, where nanosheet FETs will likely replace finFETs to meet performance, power, area, and cost (PPAC) goals. A significant architectural change is similarly being evaluated for copper interconnects at 2nm, a move that would reconfigure the way power is delivered to transistors. This approach relies on so-called buried power rails (BPRs) and... » read more

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