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Shortages Spark Novel Component Lifecycle Solutions

Fabs and equipment vendors are optimizing components in ways that previously were considered unnecessary.

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The semiconductor industry’s supply chain problems are prompting some innovative solutions and workarounds, and while they don’t solve all problems, they are improving efficiency and extending equipment lifetimes.

The shortages, which affect everything from the chips used in automotive, IoT, and consumer ICs to the equipment used to manufacture and test them — span global supply lines. They are causing process tool installation delays, equipment shortages, as well as inconsistencies in commodity and raw materials, including gases, KrF photoresists, CMP slurries, and even stainless steel. Those problems cannot be fixed quickly or easily, and they are so interconnected with other parts and processes that just adding more capacity in one area will not solve all problems. ASIC shortages may be due as much to problems with testers, photoresist filters and packaging substrates as the equipment and materials used to directly process those wafers.

“In addition to FPGAs, which have extremely long lead times, ATE uses a number of custom ASICs that have to fight for fab capacity,” said Ken Lanier, strategic business development manager at Teradyne. “We put aggressive investment in materials a long time ago and have been able to maintain reasonable lead times for our customers. We have a lot of people tasked with getting material when we need it.”

Ironically, the very tools that are enabled by semiconductor technology — AI, machine learning, digital twins, etc. — will be the ones that enable improved fab-packaging coordination, identify yield problems faster, get supply chains under control, and help the industry attain outstanding growth in a workforce constrained environment.

Nate Baxter, president of Tokyo Electron America, pointed to the company’s incorporation of digital tools in IC design, process equipment, metrology (virtual and hardware), and explained how those tools are used in the company’s centers of excellence, like its U.S. R&D, manufacturing and tool integration headquarters in Albany, NY. He said the company performs EUV lithography, FEOL, BEOL and heterogenous integration for packaging at the center, and that TEL equipment currently utilizes more than 15,000 sensors to enable faster process diagnostics, advanced process control, and data analytics.

Fig.1: To attain industry growth projections, fabs are adopting technologies that enable higher yield, productivity and smart manufacturing. Source: TEL, SEMI ISS

Fig. 1: To attain industry growth projections, fabs are adopting technologies that enable higher yield, productivity and smart manufacturing. Source: TEL, SEMI ISS

At the recent Advanced Semiconductor Manufacturing Conference (ASMC), several talks addressed the use of machine learning and AI in fabs to improve yield, tool performance and operational efficiency. At the tool level, advanced modeling is improving processes, inventory management and component utilization. In a wafer processing tool, for instance, the lifecycle of a particular component can vary based on the process temperature, chemistry and other factors.

“Semiconductor tools see large variation in process conditions between customer to customer, tool to tool, and location of components within the tool. These factors all affect the reliability of the parts significantly. For example, two pneumatic valves — one exposed to harsh environmental conditions, the second one operating under established environment conditions within the same tool — can have different lifetimes,” explained Swajeeth Panchangam, reliability engineer at Lam Research.

Lam developed a new reliability model for component lifecycle, which in this case determined the same O-ring can reliably process 40% fewer wafers when subjected to a higher temperature process relative to a lower process temperature. Panchangam noted such a model helps engineers better plan for the required inventory and schedule preventive maintenance based on real-world component modeling.

In some cases, engineers substantially modify their processes to improve yield and the quality of chips being produced, which has a welcome benefit of longer component life. Micron’s 300mm memory fab was experiencing customer returns that were traced to an incomplete bit-line etch caused by airborne molecular contamination in an inductively coupled plasma etcher.

“We developed a new continuous plasma process (CPP) etch that eliminated pressure stabilization between several etch steps, along with an improved waferless chamber clean (WCC) to eliminate systematic yield excursions and eliminate the customer returns from this failure mechanism,” said Jeff Ye, distinguished member of technical staff at Micron.

Maximizing component and tool reliability
Component lifecycle modeling is difficult to perform due to the varied process conditions that wafers encounter.

“There is a strong need for a systematic guideline on how to model semiconductor component lifetimes using field data,” said Lam’s Panangam. He noted that in estimating the lifetime of components, engineers generally use empirical models. The problem is these tend to be conservative, reducing component lifetimes with unnecessary change-outs, and increasing costs due to more frequent parts replacements and system downtime. He also said that superior lifecycle modeling enables optimal preventive maintenance scheduling and inventory stocking of exactly what is needed, when it is needed. Fabs today expect tool availability in the 90% range.

“We propose a model that uses field data, segregates failure modes, and comprehends the physics of root cause failures (see figure 2),” said Panagam. “We identify the operating conditions on the new application and see if failure mechanisms are changing or remain the same.”

The case study is of an O-ring which is a ceiling component between remote plasma clean kit and isolation valve above the showerhead in the distribution tube of the remote plasma clean of an etcher (see figure 3).

The existing process, with aggressive process chemistry and temperature, takes place at higher temperatures in the new process. The stochastic model (Coffin-Manson life stress model) estimates lifetime distribution at the new operating temperature. A cost function was used to determine the optimal time for O-ring replacement. (The engineering team reported process time in hours to replace the part, even though the number of wafers processed was actually tracked, to protect the customer’s data.) Panangam’s team determined the failure mode (O-ring wear-out due to chemical attack) was the same, but the optimal lifetime for the O-ring was 2,500 hours versus 4,000 hours at the lower, former process temperature. The results help to schedule the appropriate PM interval for this process and maintain sufficient part inventory. “Now, when we have to make a call regarding a component, the model and cost function guides potential replacement in a production environment,” Panagam said.

Fig. 2: The optimal replacement cycle is based on stochastic modeling and reliability analysis under new thermal load. Source: Lam Research, SEMI ASMC

Fig. 2: The optimal replacement cycle is based on stochastic modeling, reliability analysis of failure modes and actions, and a cost function. Source: Lam Research, SEMI ASMC

O-Ring Wear-out in Remote Plasma Clean Kit of Etcher

Fig. 3: The RPC kit replacement cycle changed from 4,000 to 2,500 hours (wafer equivalents) with the higher thermal load based on field data. Source: Lam Research, SEMI ASMC

Fig. 3: The RPC kit replacement cycle changed from 4,000 to 2,500 hours (wafer equivalents) with the higher thermal load based on field data. Source: Lam Research, SEMI ASMC

Life cycle model, cost function provides O-ring replacement time
Reliability and process engineers occasionally determine that field failures are caused by systematic tool problems. This second example shows how an existing process was re-engineered to address the root cause of field failures, which ended up significantly improving process throughput and reducing part replacement cost.

At its DRAM facility in Manassas, Va., Micron developed a new continuous plasma process on its 300mm ICP etcher with an improved waferless chamber clean (WCC). The company was experiencing a small number of memory device failures and failing die were concentrated at the wafer centers (see figure 4). The engineering team hypothesized that the defects may be caused by debris falling from the ICP etch injector onto the wafer during times when plasma DC bias was not on.

“We had been struggling to fix this issue for years with various process improvements, but we decided to introduce a continuous plasma process idea and also a new waferless chamber clean (WCC) to fix the problem forever,” said Micron’s Ye, who presented the new process at SEMI’s recent ASMC.

The airborne molecular contamination problem was causing unnecessary tool downtime (to replace the injector, which was reworked), but most importantly, customer device returns. The integrated, multi-step etch and chamber clean has some 20 steps. For the new process, Ye’s team used 300mm prime wafers for in-line characterization and probe, with SEM/EDX to identify contaminants, and TEM to examine bit-line CD measurements and profiles. Micron decided to implement a continuous plasma etch process because the stability steps in between trim etch, hardmask 1, 2, etc., were causing contamination.

“Like a refrigerator, it does not help to shut it off and turn back on, and the plasma etch chamber is similar,” said Ye. “That led to the continuous plasma process (CPP), and a change in the waferless clean from low pressure to higher pressure plasma to activate more radicals in the plasma for superior fluorocarbon removal. The WCC consists of three steps — aggressive plasma etch, O2 burn, then a dielectric conditioning step to coat the chamber,” said Ye. “We adjusted the inner-to-outer gas injector ratio to better remove debris buildup on the injector wall.”

Final process recipe parameter adjustments led to uniform bit-line etch profiles. Micron’s result showed a 1% yield improvement, substantial tool throughput gains due to 8% shorter raw process time, less tool downtime for yield excursions, and reduced cost for new and reworked gas injectors for the ICP etcher.

“Now we do not need to replace the injector very often, have fewer yield excursions, have superior bit-line control and profiles (see figure 5), and avoid return material authorizations from our customers,” Ye said. “We will transfer this new, best-known method (see figure 6) to the advanced technology nodes.”

Fig. 4: Wafer center contamination was causing memory bitline failures caused by incomplete etch. Source: Micron, SEMI ASMC

Fig. 4: Wafer center contamination was causing memory bitline failures caused by incomplete etch. Source: Micron, SEMI ASMC

Fig. 5: Improved bitline profiles were the result of continuous chamber plasma etch, optimized injector flow and optimized conditioning prior to the process wafer etch. Source: Micron, SEMI ASMC

Fig. 5: Improved bitline profiles were the result of continuous chamber plasma etch, optimized injector flow and optimized conditioning prior to the process wafer etch. Source: Micron, SEMI ASMC

Fig. 6: The new process eliminates stabilizing transitions between etch steps and optimized the WCC to clean more byproduct for longer component life. Source: Micron, SEMI ASMC

Fig. 6: The new process eliminates stabilizing transitions between etch steps and optimized the WCC to clean more byproduct for longer component life. Source: Micron, SEMI ASMC

Conclusion
The industry is employing more and more aspects of smart manufacturing, including new models for estimating component life and diagnostics using multiple tool sensors to get early indications of process or yield problems. Engineering solutions from the tool to the fab level will incorporate more advanced modeling, machine learning and feedback mechanisms to solve problems faster and keep tools and fabs producing good devices.

References

  1. S. Panchangam and K. Gowdaru, “Stochastic Based Reliability Model for Optimal Scheduled Maintenance of Semiconductor Process Tools, SEMI ASMC, May 2022.
  2. J. Ye, J. Lee and M. Davis, “Continuous Plasma Etch Process with Waferless Chamber Clean Optimization for Defect Reduction by Eliminating Center Injector Shading,” SEMI ASMC, May 2022.


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