Mark LaPedus

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Mark LaPedus is Executive Editor for manufacturing at Semiconductor Engineering.

Author's Latest Posts

Manufacturing Bits: March 31
By Mark LaPedus - 31 Mar, 2015 - Comments: 0

Shish kebab nano necklaces Using a directed self-assembly (DSA) process, Georgia Institute of Technology has developed a method to make nanometer-scale, chip-based necklaces. The technique could enable organic-inorganic structures, which resemble a tiny shish kebab or a centipede. The structures are made with various materials, such as semiconductors, magnetics, ferroelectrics and others. ... » read more

Challenges Mount For Patterning And Masks
By Mark LaPedus - 30 Mar, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Uday Mitra, vice president and chief technology officer for the Etch Business Unit at [getentity id="22817" e_name="Applied Materials"]; Pawitter Mangat, senior manager and deputy director for EUV lithography at [getentity id="22819" comment="GlobalFoundries"]; Aki Fujimura, chief executive at [getentity id="228... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 27 Mar, 2015 - Comments: 0

Intel is in talks to buy Altera, according to The Wall Street Journal. If a deal is reached, Intel would enter the FPGA market amid a slowdown in its core processors business. Intel would also secure its largest foundry customer in Altera. For years, Altera’s sole foundry was TSMC. Then, not long ago, Altera selected Intel as its foundry partner for 14nm. TSMC still handles 20nm and above wor... » read more

Manufacturing Bits: March 24
By Mark LaPedus - 24 Mar, 2015 - Comments: 0

Mouse brains to multi-beam At the recent SPIE Advanced Lithography conference, Sematech provided an update on its multi-beam, e-beam inspection program. The goal is to develop a next-generation inspection tool, which could be faster than traditional e-beam inspection and could one day displace brightfield inspection. “Optical inspection is having trouble detecting particles that are small... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 20 Mar, 2015 - Comments: 0

For years, Altera’s sole foundry was TSMC. Then, not long ago, Altera selected Intel as its foundry partner for 14nm. TSMC still handles 20nm and above work for Altera. Now, Altera will soon select a foundry partner for 10nm. “Altera will make a decision on which foundry partner it will choose for 10nm finFET at the end of 1Q15, noting it will decide between Intel and TSMC,” said John Vin... » read more

Searching For 3D Metrology
By Mark LaPedus - 19 Mar, 2015 - Comments: 3

In the previous decade, chipmakers made a bold but necessary decision to select the [getkc id="185" kc_name="finFET"] as the next transistor architecture for the IC industry. Over time, though, chipmakers discovered that the finFET would present some challenges in the fab. Deposition, etch and lithography were the obvious hurdles, but chipmakers also saw a big gap in metrology. In fact,... » read more

Challenges Mount For Patterning And Masks
By Mark LaPedus - 19 Mar, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Uday Mitra, vice president and chief technology officer for the Etch Business Unit at [getentity id="22817" e_name="Applied Materials"]; Pawitter Mangat, senior manager and deputy director for EUV lithography at [getentity id="22819" comment="GlobalFoundries"]; Aki Fujimura, chief executive at [getentity id="228... » read more

5 Issues Under The SPIE Radar
By Mark LaPedus - 19 Mar, 2015 - Comments: 0

As usual, the recent SPIE Advanced Lithography Conference was a busy, if not an overwhelming, event. At the event, there were endless presentations on the usual subjects, such as design, patterning, metrology and photoresists. And as in past years, one left the event with more questions than answers. At this year’s event, the most obvious question was (and still is) clear: Will extreme ult... » read more

Issues And Options At 5nm
By Mark LaPedus - 19 Mar, 2015 - Comments: 0

While the foundries are ramping up their processes for the 16nm/14nm node, vendors are also busy developing technologies for 10nm and beyond. In fact, chipmakers are finalizing their 10nm process offerings, but they are still weighing the technology options for 7nm. And if that isn’t enough, IC makers are beginning to look at the options at 5nm and beyond. Today, chipmakers can see a p... » read more

Manufacturing Bits: March 17
By Mark LaPedus - 17 Mar, 2015 - Comments: 0

EUV source firm seeks help In 2012, a startup called Zplasma came out of stealth mode and introduced its first technology—a next-generation power source for extreme ultraviolet (EUV) lithography. But after much fanfare and hope, Zplasma has been unable to commercialize its EUV source technology. The company has also been unable to attract a development partner or outside funding. And t... » read more

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