Author's Latest Posts


Double Patterning Custom Design And Debug


Litho-Etch-Litho-Etch (LELE) double pattern (DP) processing affects many aspects of the design flow at/below the 20 nm node level. This can be very disruptive for the custom designer, impacting basic cell design strategy, layout rules and debug as well as parasitic extraction. This paper discusses how to deal with these impacts, avoid common design mistakes, and debug quickly and accurately. ... » read more

Full-Circuit ADC Verification With Analog FastSPICE


Analog to Digital Converters (ADCs) are critical components in high-speed, high-resolution applications where an analog or RF signal has to be processed, stored, or transported in digital form. ADC performance requirements vary by application and include resolution, dynamic range, linearity, power consumption, speed, bandwidth, SNDR (Signal-to-Noise and Distortion Ratio), and ENOB (Effective Nu... » read more

Power Management Techniques For Smart Grid Devices


Energy efficiency is a top concern among developers building connected devices for the smart grid. Initially, the application-centric approach to building a device was used. But today, with sophisticated hardware power management features available on most modern processors, this is no longer the case. What’s needed is an OS-level approach that allows developers to take advantage of the full ... » read more

DFM-Compliant IP: Why You Need It, How You Get It


Customers want their designs to have the best yields from the foundry. When those designs include external IP, customers expect and demand that the IP has been optimized with the latest Design For Manufacturing (DFM) technologies to minimize variability and ensure manufacturability. IP vendors must collaborate with the foundries and EDA companies to ensure IP DFM compliance and optimization. Th... » read more

Accelerating Networking Products To Market Using Ethernet VirtuaLAB


A larger number of ports, expanding throughput, decreasing latency and overall improvement in security and ease-of-use are making today’s network switches and routers among the largest IC designs ever developed, reaching beyond a half billion gates. Verification of such complex IC designs, before silicon availability, is a daunting task. A fast, accurate, easy-to-use solution, VirtuaLAB bring... » read more

Internet Of Things Design Considerations For Embedded Connected Devices


Embedded connectivity has been around since the early days of M2M. But what is new are the many complexities and emerging standards embedded system developers need to know if they are to design the latest IoT device. This paper delves into many of the key considerations developers need to know and discusses the critical areas of IoT security and connectivity along with the importance of a prove... » read more

Full AMS Design Flow For The IoT


By Nicolas Williams and Jeff Miller The pressure for a new generation of (analog/mixed-signal) AMS design capabilities has been accelerated by the sudden demand for Internet of Things (IoT). These inexpensive devices are used in an expanding array of scenarios on the edge of the network — thus the demand for an AMS design environment that is affordable and easy to use, but powerful enough ... » read more

Full-Flow Tool Suite For Both Custom Analog And Mixed-Signal Designs


The Tanner EDA AMS IC design flow offers a cohesive, integrated mixed-signal design suite that is ideally suited to IoT and project-based design with its extremely short cycle times and sensitivity to cost. Learn more about the Tanner AMS solution in this white paper. To read more, click here. » read more

MEMS Capacitance Extraction With Calibre xACT-3D Software


The growing use of MEMS in today's complex products requires new approaches to capacitance calculation to ensure companies can meet their time-to-market targets while producing products that meet performance and reliability expectations. Freescale Semiconductor and Mentor Graphics collaborated to demonstrate that Calibre xACT-3D software provides a robust method for extracting node-to-node capa... » read more

From Simulation To Emulation


This paper introduces an acceleration-ready UVM framework and explains why it is needed, how to create it, and what its benefits are. By following the principles presented here, users will be able to write block-level UVM environments that can be reused directly in emulation. This approach has provided remarkable results in various customer environments, yielding a 50 to 5000X performance gain ... » read more

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