Author's Latest Posts

Rethinking Your Approach To Radiation Mitigation
By Mentor, a Siemens Business - 03 Jun, 2020 - Comments: 0

Formal verification and automation provide an effective, high quality, and repeatable process for fault analysis, protection, and verification for FPGA designs used in high radiation environments. This paper describes an automated systematic approach based on formal verification structural and static analysis that identifies design susceptibility to radiation induced faults. To read more, clic... » read more

Early Detection Of Power/Ground Shorts Speeds Time To Tapeout
By Mentor, a Siemens Business - 27 May, 2020 - Comments: 0

Early detection of power/ground shorts lets design teams fix errors during implementation, avoiding time-consuming design data merging and full-chip physical verification. The Calibre platform provides fast, automated power/ground checking using abstract LEF/DEF input, significantly reducing the time and resources needed to ensure these violations are removed prior to tapeout. To read more, ... » read more

UPF 1.0, UPF 2.0, UPF 2.1, UPF 3.0, And Now UPF 3.1
By Mentor, a Siemens Business - 13 May, 2020 - Comments: 0

UPF is the fastest evolving IEEE standard, and UPF 3.1 is a major milestone in its evolution. This paper provides an in-depth analysis and relevant examples of all the new features introduced in UPF 3.1 along with semantic differences with earlier versions. It also highlights migration challenges to help users migrate from existing power formats to UPF 3.1. To read more, click here. » read more

IC Test Solutions For The Automotive Market
By Mentor, a Siemens Business - 06 May, 2020 - Comments: 0

The amount of electronic content in passenger cars continues to grow rapidly, driven mainly by the integration of various advanced safety features, which will increase further with the move towards fully autonomous vehicles. It is critical that these safety-related devices adhere to the highest possible quality and reliability requirements formalized in the ISO 26262 standard that is being rapi... » read more

Porting Vivado HLS Designs To Catapult HLS Platform
By Mentor, a Siemens Business - 22 Apr, 2020 - Comments: 0

High-Level Synthesis (HLS) offers significant benefits when developing algorithms and intellectual property (IP) blocks for implementation in digital logic solutions such as Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASICs). FPGA vendors offer HLS tools and using those increases flexibility and productivity over traditional hardware description language ... » read more

Terminal Boundary Dictates Power-Aware Macros
By Mentor, a Siemens Business - 08 Apr, 2020 - Comments: 0

This paper identifies and resolves the fundamental problems of integrating, hardening and verifying soft and hard macros in larger systems with a power aware DVIF perspective. To read more, click here. » read more

Solving the E/E Dilemma of Electric And Autonomous Vehicles
By Mentor, a Siemens Business - 01 Apr, 2020 - Comments: 0

As automotive manufacturers and suppliers develop advanced technologies to realize the trends of autonomy, connectivity, electrification, and shared mobility, they are encountering a number of dilemmas as each trend drives different aspects of vehicle development. This paper will focus on the E/E design challenges created by electric and autonomous vehicles, and describe a multi-domain architec... » read more

Reducing IR And EM Issues With Automated Via Insertion
By Mentor, a Siemens Business - 25 Mar, 2020 - Comments: 0

IR drop and EM issues are significant performance and reliability detractors at advanced nodes. Adding vias is the most effective means of correction, but traditional custom scripts are difficult and time-consuming, and do not guarantee correct-by-construction vias. The Calibre YieldEnhancer PowerVia utility uses manufacturing requirements to perform automated insertion of DRC/LVS-clean vias. R... » read more

Machine Learning At The Edge
By Mentor, a Siemens Business - 11 Mar, 2020 - Comments: 0

Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much power, and even generic machine learning accelerators can be overbuilt and are not optimal for power. In this paper, learn about creating new power/memory efficient hardware architectures to meet n... » read more

AI Chip DFT Techniques For Aggressive Time-To-Market
By Mentor, a Siemens Business - 10 Mar, 2020 - Comments: 0

AI chips have aggressive time-to-market goals. Designers can shave significant time off of DFT and silicon bring up using the techniques described in this paper. Leading AI semiconductor companies have already had success with Tessent DFT tools. To read more, click here. » read more

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