Systems & Design

Porting Vivado HLS Designs To Catapult HLS Platform

How to regain the flexibility of moving a design to another technology.


High-Level Synthesis (HLS) offers significant benefits when developing algorithms and intellectual property (IP) blocks for implementation in digital logic solutions such as Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASICs). FPGA vendors offer HLS tools and using those increases flexibility and productivity over traditional hardware description language (HDL) flows. But employing FPGA vendor-specific tools can limit the portability of the design outside of their ecosystem. To regain the flexibility of targeting a design to another technology requires porting the design from the vendor’s HLS environment into an HLS environment that supports any ASIC or FPGA technology.

This white paper explores how to port an existing HLS design developed within the Xilinx Vivado HLS environment into Mentor’s Catapult HLS Platform. To read more, click here.

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