Author's Latest Posts


Taking 2.5D/3DIC Physical Verification To The Next Level


As package designs evolve, so do verification requirements and challenges. Designers working on multi-die, multi-chiplet stacked configurations in 2.5/3D IC designs can use Calibre 3DSTACK physical verification checks to verify die alignments for proper connectivity and electrical behavior. The Calibre 3DSTACK precheck mode enables design teams to find and correct basic implementation mistakes ... » read more

Veloce Prototyping Solutions Accelerate Verification Of HPC AI-Enabled SoCs


This white paper goes through the journey of understanding how to meet quality requirements and accelerate time-to-market for your company’s latest flagship high performance computing (HPC) artificial intelligence (AI)-enabled system-on-chip (SoC) design. The starting point in the journey explores the use cases for designs illustrating the impact HPC AI-enabled systems and resources have on o... » read more

Streaming Scan Network: An Efficient Packetized Data Network For Testing Of Complex SoCs


Originally presented at the 2020 International Test Conference by Siemens and Intel authors, this paper describes the Tessent Streaming Scan Network technology and demonstrates how this packetized data network optimizes test time and implementation productivity for today’s complex SoCs. The author-submitted version of the IEEE paper is reprinted here with permission. Authors: Jean-Françoi... » read more

Effectively Addressing The Challenge Of Securing Connected And Autonomous Vehicles


Vehicles are becoming the most sophisticated connected objects in the ‘Internet of Things’. As vehicles integrate functionality that will enable a fully autonomous future, the attack surface grows substantially. Combined with remote connectivity at multiple points, the clock is ticking in a race to improve cybersecurity in all types of vehicles to ensure that all stakeholders, but particula... » read more

Batch Filters: A Better, Faster Way To Filter Large DRC Results Databases


Reviewing massive DRC results databases (RDBs) can be a time-consuming stage in traditional debug flows, due primarily to the loading, filtering, and display times associated with these large datasets. Finding the most effective approach to filtering results data is important to optimize both results debug time and resource usage. While smaller databases that load quickly in GUI applications ca... » read more

Aprisa Place-And-Route For Low-Power SoCs


The Aprisa digital design software helps designers address the many challenges of low-power designs. Aprisa is the most flexible IC place-and-route tool on the market—it accepts all industry-standard power formats, has excellent correlation to third-party signoff tools, and is easy to install, set up, and use. With effective technology and impressive usability, the Aprisa software ensures cos... » read more

Reversible Chain Diagnosis


For advanced technologies, the industry is seeing very complicated silicon defect types and defect distribution. One consequence is that scan chain diagnosis becomes more difficult. To improve the resolution of scan chain diagnosis, Tessent Diagnosis can use new scan chain test patterns to leverage a reversible scan chain architecture. This paper describes the novel scan chain architecture t... » read more

How To Reduce The Impact Of The Global Microcontroller Shortage On ECU Software Development


The COVID-19 pandemic had a massive impact on all facets of business and commerce, as widespread supply chain disruptions rippled through every industry. Multiple factors collided to create a global microcontroller shortage that is now impacting the automotive industry, and is forcing developers to redesign Electronic Control Units (ECUs) using alternative Microcontrollers (MCUs) and to otherwi... » read more

Microchip Sees Significant Productivity Gains In Mature-Node Custom IC Design With In-Design Signoff DRC


Microsemi pioneered the design of innovative chips that are used for multiple purposes across a variety of industries, using both mature and advanced process nodes. In mature node custom design implementation, layout designers still spend a significant amount of their valuable time fixing DRC errors—time that could be more beneficially spent ensuring their designs meet their PPA goals. By rep... » read more

Introducing mPower


Power integrity analysis evaluates circuits to determine if they will provide their designed/intended performance and reliability as implemented. Designers must be able to verify analog and digital power integrity from the RTL/gate-level through die-level integrations up to the package and board system-level. The mPower toolset is an innovative power integrity verification solution that brings ... » read more

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