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Aprisa Place-And-Route For Low-Power SoCs
By Siemens EDA - 10 Nov, 2021 - Comments: 0

The Aprisa digital design software helps designers address the many challenges of low-power designs. Aprisa is the most flexible IC place-and-route tool on the market—it accepts all industry-standard power formats, has excellent correlation to third-party signoff tools, and is easy to install, set up, and use. With effective technology and impressive usability, the Aprisa software ensures cos... » read more

Reversible Chain Diagnosis
By Siemens EDA - 09 Nov, 2021 - Comments: 0

For advanced technologies, the industry is seeing very complicated silicon defect types and defect distribution. One consequence is that scan chain diagnosis becomes more difficult. To improve the resolution of scan chain diagnosis, Tessent Diagnosis can use new scan chain test patterns to leverage a reversible scan chain architecture. This paper describes the novel scan chain architecture t... » read more

How To Reduce The Impact Of The Global Microcontroller Shortage On ECU Software Development
By Siemens EDA - 03 Nov, 2021 - Comments: 0

The COVID-19 pandemic had a massive impact on all facets of business and commerce, as widespread supply chain disruptions rippled through every industry. Multiple factors collided to create a global microcontroller shortage that is now impacting the automotive industry, and is forcing developers to redesign Electronic Control Units (ECUs) using alternative Microcontrollers (MCUs) and to otherwi... » read more

Microchip Sees Significant Productivity Gains In Mature-Node Custom IC Design With In-Design Signoff DRC
By Siemens EDA - 27 Oct, 2021 - Comments: 0

Microsemi pioneered the design of innovative chips that are used for multiple purposes across a variety of industries, using both mature and advanced process nodes. In mature node custom design implementation, layout designers still spend a significant amount of their valuable time fixing DRC errors—time that could be more beneficially spent ensuring their designs meet their PPA goals. By rep... » read more

Introducing mPower
By Siemens EDA - 13 Oct, 2021 - Comments: 0

Power integrity analysis evaluates circuits to determine if they will provide their designed/intended performance and reliability as implemented. Designers must be able to verify analog and digital power integrity from the RTL/gate-level through die-level integrations up to the package and board system-level. The mPower toolset is an innovative power integrity verification solution that brings ... » read more

Manage Scaling Challenges For Silicon Success
By Siemens EDA - 12 Oct, 2021 - Comments: 0

Semiconductor companies are faced with significant challenges related to technology scaling, design scaling, and system scaling. These challenges have a broad impact on design development, manufacturing, and functional operation. This paper discusses the challenges and the specific impact of a Silicon Lifecycle Solutions approach that includes DFT, operations, and Embedded Analytics in enabling... » read more

STMicroelectronics Methodology And Process For Heterogeneous Automotive Package Design
By Siemens EDA - 06 Oct, 2021 - Comments: 0

As a leading supplier of automotive semiconductors, STMicroelectronics must continue to move fast to develop and deliver leading-edge solutions. Employing package design as part of system innovation requires the STMicroelectronics Back-End Manufacturing Technology R&D organization to embrace the key driving forces of product development. In the automotive field, package designers need to... » read more

Automated ESD Protection Verification For 2.5D And 3D ICs
By Siemens EDA - 22 Sep, 2021 - Comments: 0

While automated flows for ESD protection verification are well-established for 2D ICs, 2.5D and 3D designs present new challenges in both ESD circuit design and verification. Advanced automated ESD verification methodology accurately and effectively evaluates ESD protection in 2.5/3D IC designs. Ensuring correct and consistent ESD protection in 2.5/3D ICs raises the reliability and product life... » read more

Shortest Resistance Path Deception In ESD Protection Circuit P2P Debug
By Siemens EDA - 08 Sep, 2021 - Comments: 1

Verifying and fixing ESD protection circuit violations is an essential step in tapeout sign-off flows for today’s IC chip designs. As one of the most commonly used ESD verification flows, the point to point (P2P) flow checks the resistances of ESD discharge paths in layout designs to ensure they are within design thresholds. However, when debugging P2P violations, information such as the shor... » read more

How To Maximize Your Competitiveness In The Semiconductor Industry Using Advanced DFT
By Siemens EDA - 07 Sep, 2021 - Comments: 1

Embarking on advanced SoCs without a smart design-for-test (DFT) strategy can be harmful to your bottom line. Being competitive in today’s semiconductor market means adopting integrated, scalable, and flexible solutions to cut DFT implementation time, test costs, and time-to-market. Tessent DFT technologies, developed in partnership with industry leaders, provide the most advanced DFT and yie... » read more

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