Author's Latest Posts

Primary, Anonymous, or What?
By Siemens EDA - 09 Jun, 2021 - Comments: 0

Top level primary I/Os remain mysterious in the verification world, specifically when you consider UPF-based low power designs. In real silicon, they are usually driven by off-chip supplies; however, verification complications are multifold for RTL and gate level simulations of them. This paper studies the “simulation-impacting” features of design top IOs and the effect of each feature on v... » read more

Orchestrating An Efficient ISO 26262 Fault Campaign
By Siemens EDA - 02 Jun, 2021 - Comments: 0

The primary objective of a fault campaign is to understand whether the safety architecture sufficiently prevents random failures from violating ISO 26262 safety requirements for both commercial and passenger automobiles. To complete fault injection, faults are injected and propagated in the design to validate the functional correctness of the safety mechanisms and to classify each fault. Fault ... » read more

MaxLinear And Calibre RealTime Digital
By Siemens EDA - 26 May, 2021 - Comments: 0

MaxLinear implemented the Calibre RealTime Digital interface for fast, iterative, signoff DRC checking and fixing during floorplanning and placement. They not only reduce the total of batch DRC iterations, but also eliminate potential late-stage issues during final physical verification signoff that are exponentially harder to fix. Adopting the Calibre RealTime Digital interface enabled MaxLine... » read more

Machine Learning At The Edge
By Siemens EDA - 12 May, 2021 - Comments: 0

Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much power, and even generic machine learning accelerators can be overbuilt and are not optimal for power. In this paper, learn about creating new power/memory efficient hardware architectures to meet n... » read more

Monitor And Control Automotive Devices With Over-The-Air Updates
By Siemens EDA - 05 May, 2021 - Comments: 0

Modern vehicles are complex electronic devices that require regular over-the-air (OTA) system and software updates to ensure their correct and safe operation. This paper discusses the need for OTA and the Siemens solutions that ensure OTA updates are secure and meet all regulations and standards. To read more, click here. » read more

Enabling The Next Step In IC Test And Monitoring
By Siemens EDA - 21 Apr, 2021 - Comments: 0

Product lifecycle management (PLM) is a well-established concept across many industries that aims to manage the entire lifecycle of a product from inception through design, realization, deployment, and field service, right through to end-of-life activities such as final disposal. More recently, these principles are being applied by the semiconductor industry because electronics continue to p... » read more

Formal Verification Experiences
By Siemens EDA - 07 Apr, 2021 - Comments: 0

Several companies have used formal verification to perform silicon bug hunting. That is one of the most advanced usages of formal verification. It is a complex process that includes incorporating multiple sources of information and managing numerous success factors concurrently. This paper will present a “spiral refinement” bug hunt methodology that captures the success factors and guides t... » read more

Systematic Methodology To Solve Reset Challenges In Automotive SoCs
By Siemens EDA - 31 Mar, 2021 - Comments: 0

Modern automotive SoCs typically contain multiple asynchronous reset signals to ensure systematic functional recovery from unexpected situations and faults. This complex reset architecture leads to a new set of problems such as possible reset domain crossing (RDC) issues. The conventional clock domain and CDC verification methodologies cannot identify such critical bugs. In this paper, we prese... » read more

Exercising State Machines with Command Sequences
By Siemens EDA - 24 Mar, 2021 - Comments: 0

Almost every non-trivial design contains at least one state machine, and exercising that state machine through its legal states, state transitions, and the different reasons for state transitions is key to verifying the design’s functionality. In some cases, we can exercise a state machine simply as a side-effect of performing normal operations on the design. In other cases, the state machine... » read more

Nine Effective Features Of NVMe Verification IP For PCIe-Based SSD Storage
By Siemens EDA - 10 Mar, 2021 - Comments: 0

Non-Volatile Memory Express (NVMe) is a new software interface optimized for PCIe Solid State Drives (SSD). This paper provides an overview of the NVMe specification and examines some of its key features. We will discuss its pros and cons, compare it to other conventional technologies, and point out key areas to focus on during its verification. You will learn how NVMe Questa Verification IP... » read more

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