Author's Latest Posts

Calibre DesignEnhancer Design-Stage Layout Modification Improves Power Management Faster And Earlier
By Siemens EDA - 19 Jul, 2023 - Comments: 0

The faster a design can progress from implementation to signoff verification, the better the chances are of meeting tapeout schedules. The Calibre DesignEnhancer platform offers P&R and custom/analog design teams a fast, integrated environment for implementing Calibre-clean design modifications to reduce IR drop and EM and prepare for physical verification. Not only can designers reduce EM and ... » read more

Shift Left With Calibre To Optimize IC Design Flow Productivity, Design Quality, And Time To Market
By Siemens EDA - 21 Jun, 2023 - Comments: 0

Every IC designer strives to create a “clean,” or error-free, cell, block, chiplet, SoC, or 3DIC assembly before passing their work downstream for full sign-off verification. However, waiting until sign-off verification to find out how well you did is probably the least efficient approach to achieving production-ready layouts, impacting engineer productivity, project schedules, and hardware... » read more

Power Modules: A Four-Dimensional Design Challenge Calls For A Holistic Design And Verification Approach
By Siemens EDA - 07 Jun, 2023 - Comments: 0

A power module is a high-power switching circuit used in applications for electric vehicles, renewable energy, photovoltaics, wind power, and much more. Switching-element IGBTs and MOSFETs are used in these modules. This paper discusses different technologies and the associated design challenges to achieve complex power module requirements like high voltage resistivity up to 1700 V, high curren... » read more

Distribution Of Currents In Via Arrays
By Siemens EDA - 24 May, 2023 - Comments: 0

It has become increasingly difficult in recent years to provide adequate PDNs on a PCB. The sheer number of different voltages, combined with increased current demands, makes distributing current around the board a substantial layout challenge. This paper demonstrates that by using appropriate and accurate simulations, combined with the improved intuition that such simulations bring, it is a ch... » read more

Placement And CTS Techniques For High-Performance Computing Designs
By Siemens EDA - 10 May, 2023 - Comments: 0

This paper discusses the challenges of designing high-performance computing (HPC) integrated circuits (ICs) to achieve maximum performance. The design process for HPC ICs has become more complex with each new process technology, requiring new architectures and transistors. We highlight how the Siemens Aprisa digital implementation solution can solve placement and clock tree challenges in HPC de... » read more

Automotive Safety Island
By Siemens EDA - 03 May, 2023 - Comments: 0

The promise of autonomous vehicles is driving profound changes in the design and testing of automotive semiconductor parts. Automotive ICs, once deployed for simple functions like controlling windows, are now performing complex functions related to advanced driver-assist systems (ADAS) and autonomous driving applications. The processing power required results in very large and complex ICs that ... » read more

Pre-Layout, Post-Layout Circuit Reliability
By Siemens EDA - 26 Apr, 2023 - Comments: 0

With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification to check design reliability is no longer practical for design teams. Designers must now apply reliability verification checks throughout the design flow, from intellectual property (IP) level to full-chip level, to ensure they meet tapeout schedules while confirming design reliability... » read more

Effective Resource Utilization In PCIe Gen6: Shared Flow Control
By Siemens EDA - 12 Apr, 2023 - Comments: 0

In PCIe 6.0, the data rate has doubled from 32 GT/s to 64 GT/s. This technology is a cost-effective and scalable interconnect solution that will continue to impact data-intensive markets and applications while maintaining backward compatibility with all previous generations of PCIe. Data-intensive uses include data centers, artificial intelligence/machine learning computing, high-performance co... » read more

Navigating The Intersection Of Safety And Security
By Siemens EDA - 06 Apr, 2023 - Comments: 0

Automotive ICs can be secure without needing to be safe, but a safety critical IC cannot be safe without also being secure. Addressing the intersection of safety and security in highly complex automotive SoCs is challenging even for veteran project teams. This paper focuses on how these two domains intersect, what to consider when analyzing and implementing both safety and security architect... » read more

A Hierarchical And Tractable Mixed-Signal Verification Methodology For First-Generation Analog AI Processors
By Siemens EDA - 22 Mar, 2023 - Comments: 0

Artificial intelligence (AI) is now the key driving force behind advances in information technology, big data and the internet of things (IoT). It is a technology that is developing at a rapid pace, particularly when it comes to the field of deep learning. Researchers are continually creating new variants of deep learning that expand the capabilities of machine learning. But building systems th... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy