Author's Latest Posts


Interactive Point-To-Point Resistance Simulations


Point to point (P2P) resistance simulations calculate the effective resistance of the layout traces between points on an IC net trace, and let the designer know that there may be too much parasitic resistance from a particular net trace that would affect the reliability or performance of the circuit. However, traditional P2P simulation runs are time-consuming, and often require multiple iterati... » read more

Affordable And Comprehensive Testing Of 3D Stacked Die Devices


Developers of high-end semiconductor products who face manufacturing limitations with respect to die sizes are investing in 3D stacked die technology. These advanced designs already push current design-for-test (DFT) solutions to the limits: tool run time, on-chip area demand, test pattern count, and test time. How then, can designers manage DFT for these new 3D devices? In this paper, we outli... » read more

Enabling Model-Based Design For DO-254 Certification Compliance


The increasing prevalence and cost of projects that need to comply with the DO-254 standard is forcing companies to evaluate their development processes. This white paper shows a development approach to compliance using model-based design. It covers how a DO-254 workflow using model-based design promotes a consistent requirements-oriented project view and increases reuse of design and verificat... » read more

Ensure Functional Safety Using Siemens’ AUTOSAR Solutions


As the prevalence of automated driving, electrification, and connected vehicle applications increases, the complexity of electrical and electronic (E/E) vehicle architecture is increasing, and vehicle safety requirements are becoming more demanding. Solution architects and engineers are looking for ways to manage it all. And they can, with the help of our comprehensive AUTOSAR solution that pro... » read more

Power Methodology For Estimation And Optimization In The ASIC/SoC Flow


In this white paper, we’ll review the many steps of today’s common ASIC/SoC power methodologies and tool flows. We’ll then propose ways you can further optimize your power methodology to more quickly achieve your PPW goals. Please note, while we acknowledge that energy consumption in digital CMOS logic is a combination of dynamic power and leakage, to keep this white paper to a digestible... » read more

Verifying A DDR5 Memory Subsystem


With the increasing complexity of DDR memory models and a vast set of configurations, it has become a daunting experience for verification engineers to verify memory subsystems. With the help of DDR5 Questa VIP and its unique features, engineers can maximize their debugging capabilities and achieve their verification goals quickly and efficiently. This paper introduces the Siemens EDA DDR5 and ... » read more

Machine Learning Application For Early Power Analysis Accuracy Improvement


In this paper, we introduce a machine learning (ML) application that accurately estimates the switching power of the cells without needing the SPEF file (SPEF less PA flow). Three ML models (multi-linear regression, random forest and decision tree) were trained and tested on different industrial designs at 7nm technology. They are trained using different cells’ properties available, SPEF, and... » read more

Software Infrastructure For Silicon Lifecycle Management


Semiconductor technology continues to deliver higher levels of logic density in the era of nanometer processes. System-on-chip (SoC) teams can deliver even higher functionality when coupled with the massive integration possibilities of three-dimensional integrated circuit (3DIC) architectures. However, this growth must be matched by increases in capabilities and productivity in the collection a... » read more

Responding To The Rapid Advancement Of Cockpit Domain Controllers


Every aspect of a modern vehicle’s performance is controlled by a complex network of hardware and software. Nowhere is this more apparent than the interface between the driver and the machine, in what is known as the cockpit domain. In order to succeed in this domain of fast-paced advancement, today’s OEM needs to understand the trends in this arena, the current challenges and solutions, an... » read more

Enhance IC Reliability Design Verification With Coordinate-Based P2P And CD Checking


Coordinate-based P2P and CD checks with the Calibre PERC reliability platform enable quick early-stage design verification of ESD protection and other IC reliability issues. Using coordinate-based checking minimizes the amount of rule deck coding required, enabling design teams to start Calibre PERC P2P/CD verification very quickly, and understand and debug the results easily. Because P2P/CD ch... » read more

← Older posts Newer posts →