Author's Latest Posts

Accelerating Verification Shift Left With Intelligent Coverage Optimization
By Synopsys - 12 Oct, 2021 - Comments: 0

Functional verification dominates semiconductor development, consuming the largest percentage of project time and resources. Team members look at the rate of design bug discovery, consider anecdotal information on the types of bugs that escaped to silicon in previous projects, and use their best judgment based on their years of experience to determine when to tape out. Above all, they look at v... » read more

The 5 Essential Elements Of A Successful Software Security Initiative
By Synopsys - 06 Oct, 2021 - Comments: 0

Every organization that develops or integrates software needs a software security initiative—a blend of people, processes and tools that ensures applications and the data they process are secure. As customers, regulators, executives and boards of directors start asking for evidence of a formal approach to software security, organizations are trying to determine where to start, how to construc... » read more

Faster Analog Design Closure With Early Parasitic Analysis Flow – Part 1
By Synopsys - 22 Sep, 2021 - Comments: 0

In part 1 of this series, Denis Goinard, Director of Engineering at Synopsys, discusses how Synopsys provides a unified workflow to accurately estimate, measure, extract and simulate parasitics by bringing signoff tools into the design process, enabling faster design convergence. Click here to play the video. Note: This is a Synopsys 'video white paper.' For more video white papers, click h... » read more

GPIOs: Critical IP For Functional Safety Applications
By Synopsys - 08 Sep, 2021 - Comments: 0

The prevalence and complexity of electronics and software (EE systems) in automotive applications are increasing with every new generation of car. The critical functions within the system on a chip (SoC) involve hardware and software that perform automotive-related signal communication at high data rates to and from the components off-chip. Every SoC includes general purpose IOs (GPIOs) on its ... » read more

AppSec Risk: The Dangers And How to Manage Them
By Synopsys - 01 Sep, 2021 - Comments: 0

As software continues to deliver more features than ever before, its quality and security are increasingly crucial to the success of every organization. Building secure software makes business sense for a variety of reasons, including diminishing financial liability and improving competitive advantage. Keeping track of every software vulnerability, however, is taxing and time-consuming—and... » read more

RTL Architect: Parallel RTL Exploration With Unparalleled Accuracy
By Synopsys - 25 Aug, 2021 - Comments: 0

Increasing chip complexity and restrictive advanced node rules have made it harder for implementation tools to achieve PPA targets and node entitlements via last-mile optimizations. RTL Architect enables designers to "shift-left" and predict the implementation impact of their RTL. RTL designers, SoC integrators, and IP developers have embraced this fast, predictive technology to give them new i... » read more

10X Higher Productivity With VCS Dynamic Test Loading
By Synopsys - 11 Aug, 2021 - Comments: 0

The verification of a system-on-chip (SoC) is becoming increasingly complex, due to the multitude of functionality being implemented on a single chip. Different verification techniques are required at each level (IP, block, SoC and system) for faster verification closure. A successful verification strategy requires reuse of functional tests, faster test development and faster debug to improve t... » read more

Securing 5G And IoT With Fuzzing
By Synopsys - 04 Aug, 2021 - Comments: 0

5G will revolutionize many industries, with up to 100 times the speed, 100 times the capacity, and one-tenth the latency compared to 4G LTE. But in addition to providing superior performance, 5G expands the attack surface of apps and IoT devices that rely on this next-gen network. In addition to known security exploits, we’re bound to see unknown, novelty attacks. Fuzz testing (or fuzzing)... » read more

Parallel RTL Exploration With Unparalleled Accuracy
By Synopsys - 28 Jul, 2021 - Comments: 0

Increasing chip complexity and restrictive advanced node rules have made it harder for implementation tools to achieve PPA targets and node entitlements via last-mile optimizations. RTL Architect enables designers to "shift-left" and predict the implementation impact of their RTL. RTL designers, SoC integrators, and IP developers have embraced this fast, predictive technology to give them new i... » read more

Optimize Physical Verification Cost Of Ownership With Elastic CPU Management
By Synopsys - 07 Jul, 2021 - Comments: 0

For physical verification, advanced process technology nodes create implementation challenges. Design sizes have gotten larger and required rules from foundries have become more numerous in count (thousands) and more complex (hundreds of discrete steps). For these reasons, physical verification tools have been able to span these jobs not only across multiple CPUs on a single physical compute ho... » read more

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