Author's Latest Posts

The Next Generation of Testbench Debug Productivity
By Synopsys - 08 Jun, 2021 - Comments: 0

It is widely accepted that verification consumes at least sixty percent of time and resources on most semiconductor development projects. This statistic has been borne out by many industry surveys over the last twenty years. Verification technology has had to evolve to accommodate ever larger and more complex designs. Innovations such as constrained-random simulation and the Universal Verificat... » read more

When It Makes Sense To Perform An Open Source Audit
By Synopsys - 02 Jun, 2021 - Comments: 0

Today's software is not created so much as assembled. The parts that serve as ingredients come from a variety of sources, but mostly from the millions of open source components freely available on the internet. This has enabled a digital transformation in several industries, helping market leaders speed their time to market, lower costs, and improve innovation. But what are the licensing and... » read more

Designing Secure and Trusted Silicon Using Shift-Left in Verification
By Synopsys - 12 May, 2021 - Comments: 0

Designing secure silicon requires the design to be stable at all times, it shouldn't enter unknown states at any time to make it vulnerable from the security point of view. This paper identifies different sources of instability such as combinational feedback loop, unguarded clock and reset crossing, unguarded power crossing, etc. These instabilities can lead to unknown value propagation and hig... » read more

FPGA Prototyping: Supersizing Scale And Performance
By Synopsys - 11 May, 2021 - Comments: 0

Given the cost of re-spinning a system-on-chip (SoC), semiconductor companies have always looked for ways to verify and validate the SoC before tape-out. Prototyping using field programmable gate arrays (FPGAs) became a key methodology as part of this pre-silicon verification and validation effort. Click here to read more. » read more

Penetration Testing: A Buyer’s Guide
By Synopsys - 05 May, 2021 - Comments: 0

Data breaches continue to plague organizations—whether they’re targeted attacks from outside or malicious insiders. According to the 2020 IBM “Cost of Data Breach” report, 52% of breaches were caused by a malicious attack and the average total cost of a breach was $3.86 million. Many of these breaches are the result of combinations of errors or vulnerabilities, with attackers working th... » read more

Early, Accurate, Signoff-Correlated Power Analysis
By Synopsys - 21 Apr, 2021 - Comments: 0

Power estimation has always been a fundamental part of semiconductor development, but it has grown in importance in recent years. Virtually every application domain has power limitations that must be satisfied before a chip is fabricated. There is no effective way to fix power issues in the lab or in the field, so pre-silicon estimation must be accurate. The short development cycles for many ty... » read more

Finding And Fixing Design And Testbench Coding Errors On The Fly
By Synopsys - 06 Apr, 2021 - Comments: 0

Two things are certain in chip verification: as many bugs as possible must be found and fixed before fabrication, and this must happen as early as possible in the development process. The much-desired “shift left” in verification requires that advanced analysis and debug technologies be available to engineers from the earliest stages of the project. It is preferable that many classes of err... » read more

CISO’s Guide To Sensitive Data Protection
By Synopsys - 31 Mar, 2021 - Comments: 0

Emerging data protection and privacy laws are causing organizations to scramble to implement strategies that address regulatory compliance and data security governance. And the SolarWinds software supply chain attack, in which attackers inserted a malicious back door into its network software release that later led to sensitive data exposure, further underscores the need to secure the DevSecOps... » read more

Accelerate Custom Layout Using Custom Compiler’s User-Defined Device (UDD)
By Synopsys - 24 Mar, 2021 - Comments: 0

In this 7th video of the series, Kai Wang, Director of Engineering at Synopsys, discusses in-design electrical analysis, and why it is critical to use signoff engines to check and fix resistance, capacitance and electromigration issues during layout. Click here to access this video whitepaper. » read more

Designing ASIPs With Confidence
By Synopsys - 10 Mar, 2021 - Comments: 0

Well-designed ASIPs with a strong SDK combine C/C++ programmability with the power and performance of dedicated hardware. Product families based on ASIP platforms are often highly flexible, capable of addressing multiple market segments with the same silicon and handling updates in the field. They lean well towards software-driven verification with few penalties for late product requirement cha... » read more

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