Author's Latest Posts

Diary Of A Heartbleed
By Synopsys - 06 Dec, 2017 - Comments: 0

The Heartbleed vulnerability affects how OpenSSL implements the heartbeat protocol in TLS. In computing, a heartbeat, or a simple data message, typically determines the persistence of another machine in a given transaction; in this case, a heartbeat determines the persistence of the encryption between a client and a server. In this case, Heartbleed allows an attacker to request data more than a... » read more

Understanding How To Assess Tool Confidence Levels For ISO 26262
By Synopsys - 29 Nov, 2017 - Comments: 0

ISO 26262, the automotive functional safety standard, requires the assessment of software Tool Confidence Levels (TCLs). Some SoC designers are under the impression that all tools must be classified with a TCL1. In reality, the goal is to classify your tools accurately for your specific situation and use case. This white paper provides insight on assessing TCLs that are consistent with ISO 2626... » read more

Rapid Pattern Sequencing And Optimization With STAR Hierarchical System At STMicroelectronics
By Synopsys - 08 Nov, 2017 - Comments: 0

This white paper is the second in a series of two papers on STMicroelectronics’ experience with the Synopsys DesignWare STAR Hierarchical System. This white paper also provides insights on IEEE 1500 based network implementation, execution and analysis. It details the MASIS file’s pattern sequencing which is used for production tests and helps minimize test time. For the thermal sensor examp... » read more

STMicroelectronics’ Implementation Of The STAR Hierarchical System And IEEE 1500 Wrapping
By Synopsys - 01 Nov, 2017 - Comments: 0

This white paper discusses various IEEE 1500 architectures that STMicroelectronics has deployed using the Synopsys DesignWare STAR Hierarchical System test solution. STAR Hierarchical System allows users to optimize test time on system-on-chips that use multiple cores. The white paper provides guidelines on interface IP wrapping with IEEE 1500 to improve test time. In addition, it discusses the... » read more

A Dual-Mode Error-Correcting Code Solution For 50Gbps Ethernet
By Synopsys - 25 Oct, 2017 - Comments: 0

The increase in bandwidth is driving more innovations in the Ethernet physical layer technology to combat numerous challenges like channel loss, inter-symbol interference and more importantly error detection and correction. It is imperative to have a mechanism in place to detect and correct errors as data is transmitted and received, while maintaining small silicon area and low power consumptio... » read more

Addressing Power Integrity Challenges For SoCs
By Synopsys - 11 Oct, 2017 - Comments: 0

Power integrity has become a crucial part of the system-on-a-chip (SoC) design flow because power-related issues can affect chip timing and even lead to complete device failure. Specifically, excessive rail voltage drop (IR-drop) and ground bounce can create timing problems and electromigration effects that impact a chip's performance and reliability. Analyzing a chip's power also poses diff... » read more

Developing High-Reliability Reprogrammable NVM IP for Automotive Application
By Synopsys - 04 Oct, 2017 - Comments: 0

To help IC designers understand the complexities in developing the highest reliability non-volatile memory (NVM) IP for automotive applications, this white paper will review key considerations from design to test, including: key reliability specifications, designing-in reliability, and demonstrating reliability through characterization, qualification, and reliability testing. This paper helps I... » read more

A Simple Way To Debug IIP-Based Designs And SoCs
By Synopsys - 27 Sep, 2017 - Comments: 0

Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. This whitepaper presents the concept of debugging with “real time simulation data” using Verdi Transaction Debug Platform (protocol analyzer, waveform viewer, source code browser) and show its benefits by taking a few generic USB... » read more

Functional Safety For FPGA-Based Hardware Designs
By Synopsys - 13 Sep, 2017 - Comments: 0

Advances in design and manufacturing technology allow increased factory automation, where tasks are automatically performed by sophisticated equipment such as industrial robots. Manufacturing processes require fail-safe mechanisms to prevent human injury or costly downtime. With increasing sophistication and automation of the manufacturing processes, there is increasing need for error detection... » read more

Fuzz Testing Maturity Model
By Synopsys - 23 Aug, 2017 - Comments: 0

Fuzz testing is a highly effective technique for locating vulnerabilities in software. Malformed and unexpected inputs are delivered to the target software, and when failures occur, vulnerabilities have been located. Fuzzing is a widely recognized technique for improving the security, robustness, and safety of software. However, fuzzing is an open-ended pursuit—an infinite space problem. So, ... » read more

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