Author's Latest Posts

How To Scale Application Security Across The Enterprise
By Synopsys - 24 Apr, 2024 - Comments: 0

Enterprise organizations have hundreds of developers on numerous teams in dozens of business units. They are all working on thousands of applications, releasing software in very rapid iteration cycles. The challenges of development across all these software development life cycles, business units, and organizational silos are well known, and the sheer scale of enterprise development multiplies ... » read more

IC Compiler II: Finding The Best Floorplan, Fast
By Synopsys - 17 Apr, 2024 - Comments: 0

As designers strive to pack more and more functionality into todays’ SoC’s, design size (in terms of the number of transistors packed into a chip) is growing almost exponentially. This growth brings with it an unbounded increase in not just the technical complexity of performing the physical layout of the design due to capacity challenges, but also requires designers to make choices that ca... » read more

Unlocking PPA Benefits of Backside Routing
By Synopsys - 10 Apr, 2024 - Comments: 0

The power delivery network (PDN) is a critical part of any modern semiconductor device. Even with advanced power-saving technologies, today’s chips are hungry for power. Traditionally, power is distributed through metal layers on the same side of the substrate as the signal metal layers. This creates competition for the available layers and pushes the limits of fabrication technology to add m... » read more

Faster And Better Floorplanning With ML-Based Macro Placement
By Synopsys - 03 Apr, 2024 - Comments: 0

The chips contained in today’s consumer and commercial electronic products are staggering in size and complexity. The largest devices include central processing units (CPUs), graphics processing units (GPUs), and system-on-chip (SoC) devices that integrate many functions on a single die. Additionally, chips are expanding beyond their traditional borders with multi-die approaches such as 2.5DI... » read more

Leveraging Automotive Chip Design Techniques For Space-Borne Applications
By Synopsys - 27 Mar, 2024 - Comments: 0

Space-borne electronics must operate in an unforgiving environment with harsh conditions and little opportunity to repair failing components. A combination of functionally safe design, RHBD, and robust IP is required. Fortunately, automotive applications share many of the same challenges, and techniques to address these challenges are well established and proven. This white paper surveys the ma... » read more

Simulation With Taint Propagation For Security Verification
By Synopsys - 13 Mar, 2024 - Comments: 0

Security has arisen as a primary concern for many types of electronic devices. A wide range of malicious agents is constantly probing and looking for weaknesses to try to steal confidential information or exert unauthorized control. The need for security has been well understood and widely adopted in software for years. Techniques such as passwords, multi-factor authentication, and biometric ch... » read more

Overcoming The Challenges Of Verifying Multi-Die Systems
By Synopsys - 12 Mar, 2024 - Comments: 0

Despite clear advantages of multi-die systems, the decision to design a multi-die system rather than a traditional monolithic SoC is not easy. There are numerous new challenges that stand in the way of multi-die system realization. This white paper focuses on the verification challenges of multi-die systems, including: Addressing capacity and performance for system verification Valid... » read more

Ensure Zero Functional CDC Signoff Defects With VC SpyGlass Integrated Solution
By Synopsys - 06 Mar, 2024 - Comments: 0

This whitepaper will explain how designers can ensure zero defects seamlessly using Synopsys VC SpyGlass as a single cockpit for not just structural CDC analysis but also for complete functional analysis. We will also cover how designers can utilize a single dashboard for tracking the functional CDC signoff progress over the course of the project. Click here to read more. » read more

Advanced Design Planning In IC Compiler II
By Synopsys - 28 Feb, 2024 - Comments: 0

By Rajiv Dave, CAE Manager, Synopsys. Design exploration and planning is becoming an increasingly critical step of the design creation process as growing constraints and requirements are placed upon it. IC Compiler II has been architected from the ground up with the express focus to address the three key challenges of design planning: Capacity to handle the largest design optimally yet ... » read more

Computational Lithography Solutions To Enable High NA EUV
By Synopsys - 21 Feb, 2024 - Comments: 0

This white paper identifies and discusses the computational needs required to support the development, optimization, and implementation of high NA extreme ultraviolet (EUV) lithography. It explores the challenges associated with the increased complexity of high NA systems, proposes potential solutions, and highlights the importance of computational lithography in driving the success of advanced... » read more

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