Author's Latest Posts


Early Architecture Performance And Power Analysis Of Multi-Die Systems


A multi-die system is a semiconductor device in which multiple homogeneous or heterogeneous dies are contained within a single package. Multi-die systems have been available for select uses for years, but they are gaining wider popularity and are expected to be used in a wide variety of end applications, including high-performance computing, automotive, and mobile. There are two main factors dr... » read more

Meeting Stringent PA_SaveConfigTime In UFS Solution When M-PHY Needs Higher Reconfigure Time


The JEDEC Universal Flash Storage (UFS) has emerged as the default mobile storage solution for high-end smartphones and battery-operated devices, owing to its superior speed, performance, and power efficiency. These attributes are essential to meet users' demand for rapid transmission and reception of high-resolution media amid myriad operations. Despite these advantages, UFS's use of the MIPI ... » read more

Building A Comprehensive Multicloud Security Strategy: A Zero-Trust Approach


The traditional, perimeter-based security model is no longer sufficient in today’s dynamic, multicloud deployments. A zero-trust (ZT) security model, in which no user or system is inherently trusted, is becoming essential—it is a foundational capability that underpins security for multicloud strategies. The ZT security model operates on the principle of “Never trust. Always verify.” ... » read more

Challenges Facing The Automotive Industry Now And In The Future


The next decade may be the most exciting for the automotive industry, with carmakers, suppliers, and consumers all witnessing changes and advancements coming at breakneck speed. In fact, there will likely be more development of new technologies to power vehicles, make them safer and offer more conveniences and services in the next 10 years than in the previous 50 years. Battery-electric powertr... » read more

Accelerated Optimization With IC Compiler II


Efficient optimization is a necessary, yet challenging aspect of the physical implementation flow. IC Compiler II and the underlying physical optimization engines have been re-thought and re-architected to address these growing challenges. Click here to read more. » read more

Leveraging IBIS-AMI Models To Optimize PCIe 6.0 Designs


The exploding demand for more data driven by advancements such as artificial intelligence and machine learning has created an increase in bandwidth (BW) for interconnects for different systems and hardware components such as graphic cards, network cards, storge devices, CPUs, memories, and many more. PCIe is the leading high-speed serial communication protocol for connecting such hardware compo... » read more

Curvilinear Mask Patterning For Maximizing Lithography Entitlement


Curvilinear Mask Patterning is a cutting-edge lithography technique that promises to maximize lithography entitlement by addressing complex design challenges and critical yield limiters. However, its widespread deployment has been limited by significant computational challenges. This paper includes practical solutions to overcome the computational challenges associated with this technique, as w... » read more

Automated Constraint Management For Faster Designer Productivity


Constraints management helps shorten the designer’s manual constraints transformation effort across the design cycle with automated constraints management flows. The management of constraints refers to tasks that are not associated with verifying the correctness of constraints, nor associated with the generation of constraints, but with the transformation of constraints from one form to anoth... » read more

2023 Open Source Security And Risk Analysis Report


The annual “Open Source Security and Risk Analysis” (OSSRA) report, now in its 8th edition, examines vulnerabilities and license conflicts found in roughly 1,700 codebases across 17 industries. The report offers recommendations for security, legal, risk, and development teams to better understand the security and risk landscape accompanying open source development and use. Click here to ... » read more

ESD Co-Design For 224G And 112G SerDes In FinFET Technologies


In addressing the challenges of enhancing ESD resilience for high-speed SerDes interfaces, it's crucial to ensure the implementation of appropriate ESD protection measures. This is particularly vital during the device's lifecycle from the conclusion of silicon wafer processing to system assembly, a phase during which electronic devices are highly susceptible to Electrostatic Discharge (ESD) dam... » read more

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