Author's Latest Posts


Achieving Consistent RTL Power Accuracy


Are you struggling to accurately estimate RTL power consumption early in your design process? RTL power estimation can be inaccurate due to the complexity of the designs, the various power domains, and the use of multiple tools in the design process. Designers can make effective power-performance-area tradeoffs early by using a holistic methodology that includes both architectural and micro-arc... » read more

Achieving Your Low Power Goals With Synopsys Ultra Low Leakage IO


The demand for low power design has intensified with shrinking geometries. At the same time, innovation in battery operated, handheld devices has increased the design complexity by adding more and more functionality. The focus is on power-optimized designs while maintaining low cost and reduced risk. Designers face these complex and contradictory challenges: developing products with the lowest ... » read more

How The Doubling Of Interconnect Bandwidth With PCI Express 6.0 Impacts IP Electrical Validation


As a result of the innovations taking place in CPUs, GPUs, accelerators, and switches, the interface in hyperscale datacenters now requires faster data transfers both between compute and memory and onto the network. PCI Express (PCIe) provides the backbone for these interconnects and is used to build protocols such as Computer Express Link (CXL) and Universal Chiplet Interconnect Express (UCIe... » read more

Accelerating Coverage Closure With AI-Based Verification Space Optimization


Coverage is at the heart of all modern semiconductor verification. There is no maxim more fundamental to this process than “if you haven’t exercised it, you haven’t verified it.” Although covering a particular aspect of a chip design does not guarantee that all bugs are found — bug effect propagation and checker quality are also key factors — it is certainly true that bugs cannot po... » read more

Meeting The Major Challenges Of Modern Memory Design


Memory lies at the heart of every electronics application, and demand is growing all the time. Users want ever greater capacity, throughput, and reliability. At the same time, time to market (TTM) goals and competitive pressures mandate that memories be developed in ever shorter project schedules. These requirements put enormous pressure on designers of discrete memory chips, memory dies in 2.5... » read more

Threat Modeling, Decoded — Charting The Security Journey


Connected systems are part of the modern world. There is virtually no aspect of life that is not available online, from shopping and booking tickets to dating, banking, and attending medical appointments. And these trends show no sign of stopping. On the contrary, many services are moving to digital-first or digital-only models, and every day, new products— from toasters to autonomous vehicle... » read more

2023 Open Source Risk In M&A By The Numbers


Learn how an open source audit can reduce your security risk Here’s what we know: Most of today’s codebases contain open source components. Vulnerabilities and licensing issues in codebases are as pervasive as open source itself. Unpatched software vulnerabilities are one of the biggest cyberthreats organizations face. Failure to comply with open source licenses can put... » read more

How Low Can You Go? Pushing The Limits Of Transistors


Deep low voltage enablement of embedded memories and logic libraries to achieve extreme low power: Rising demand for cutting-edge mobile, IoT, and wearable devices, along with high compute demands for AI and 5G/6G communications, has driven the need for lower power systems-on-chip (SoCs). This is not only a concern for a device’s power consumption when active (dynamic power), but also when... » read more

How The Doubling Of Interconnect Bandwidth With PCI Express 6.0 Impacts IP Electrical Validation


As a result of the innovations taking place in CPUs, GPUs, accelerators, and switches, the interface in hyperscale datacenters now requires faster data transfers both between compute and memory and onto the network. PCI Express (PCIe®) provides the backbone for these interconnects and is used to build protocols such as Computer Express Link (CXL™) and Universal Chiplet Interconnec... » read more

How To Build A Rock-Solid Software Security Initiative


Application security testing is the starting block, not the finish line. While a critical component of every security program, the “penetrate and patch” approach is not a strategy. You need a complete program to lower risk exposure, measure progress, and demonstrate results. The most effective AppSec programs—or software security initiatives—are fine-tuned to their respective organiz... » read more

← Older posts Newer posts →