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Cooling Technology For Next Gen Power Electronics
By Technical Paper Link - 04 Sep, 2024 - Comments: 0

A new technical paper titled "Advances in Two-Phase Cooling for Next Power Electronics Converters" was published by researchers at ROMA TRE University, ENEA Casaccia Research Center and Sapienza University. "The proposed arrangement allows a greater extraction of the heat at a very low flow rate of the cooling fluid, even with standard industrial-grade heat-sinks, which motivates the use of ... » read more

Large-Scale VFETs With Ultra-Short Channel Length And High Performance
By Technical Paper Link - 04 Sep, 2024 - Comments: 0

A new technical paper titled "Large-scale sub-5-nm vertical transistors by van der Waals integration" was published by researchers at Hunan University. "Here, we demonstrate a layer-by-layer transfer process of large-scale indium gallium zinc oxide (IGZO) semiconductor arrays and metal electrodes, and realize large-scale VFETs with ultra-short channel length and high device performance," sta... » read more

Hardware Security: One-Key Premise of Logic Locking
By Technical Paper Link - 30 Aug, 2024 - Comments: 0

A new technical paper titled "Late Breaking Results: On the One-Key Premise of Logic Locking" was published by researchers at Synopsys. Abstract "The evaluation of logic locking methods has long been predicated on an implicit assumption that only the correct key can unveil the true functionality of a protected circuit. Consequently, a locking technique is deemed secure if it resists a good ... » read more

Analysis of the Errors of High-Fidelity Two-Qubit Gates in Silicon Quantum Dots (UNSW et al.)
By Technical Paper Link - 28 Aug, 2024 - Comments: 0

A new technical paper titled "Assessment of the errors of high-fidelity two-qubit gates in silicon quantum dots" was published by researchers at UNSW, Diraq, Sandia National Laboratories, Keio University, Leibniz-Institut für Kristallzüchtung and others. Abstract "Achieving high-fidelity entangling operations between qubits consistently is essential for the performance of multi-qubit syst... » read more

DL Compiler for Efficiently Utilizing Inter-Core Connected AI Chips (UIUC, Microsoft)
By Technical Paper Link - 28 Aug, 2024 - Comments: 0

A new technical paper titled "Scaling Deep Learning Computation over the Inter-Core Connected Intelligence Processor" was published by researchers at UIUC and Microsoft Research. Abstract "As AI chips incorporate numerous parallelized cores to scale deep learning (DL) computing, inter-core communication is enabled recently by employing high-bandwidth and low-latency interconnect links on th... » read more

GPU Microarchitecture Integrating Dedicated Matrix Units At The Cluster Level (UC Berkeley)
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "Virgo: Cluster-level Matrix Unit Integration in GPUs for Scalability and Energy Efficiency" was published by UC Berkeley. Abstract "Modern GPUs incorporate specialized matrix units such as Tensor Cores to accelerate GEMM operations central to deep learning workloads. However, existing matrix unit designs are tightly coupled to the SIMT core, limiting the size a... » read more

A HW-Based Correct Execution Environment Supporting Virtual Memory (Korea U., KAIST)
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "A Hardware-Based Correct Execution Environment Supporting Virtual Memory" was published by researchers at Korea University, Korea Advanced Institute of Science and Technology and other universities. Abstract "The rapid increase in data generation has led to outsourcing computation to cloud service providers, allowing clients to handle large tasks without inve... » read more

Benefits Of The Ultra-Low Leakage Currents from IGZO TFTs For Neuromorphic Applications
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "A tunable multi-timescale Indium-Gallium-Zinc-Oxide thin-film transistor neuron towards hybrid solutions for spiking neuromorphic applications" was published by researchers at imec, CSIC Universidad de Sevilla, and Sungkyunkwan University. Abstract "Spiking neural network algorithms require fine-tuned neuromorphic hardware to increase their effectiveness. Such ... » read more

LLMs In The High-Level Synthesis Design Flow
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "Are LLMs Any Good for High-Level Synthesis?" was published by researchers at University of Arizona. Abstract "The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS proces... » read more

Characterizing Three Supercomputers: Multi-GPU Interconnect Performance
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "Exploring GPU-to-GPU Communication: Insights into Supercomputer Interconnects" was published by researchers at Sapienza University of Rome, University of Trento, Vrije Universiteit Amsterdam, ETH Zurich, CINECA, University of Antwerp, IBM Research Europe, HPE Cray, and NVIDIA. Abstract "Multi-GPU nodes are increasingly common in the rapidly evolving landscape... » read more

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