Author's Latest Posts

In-Depth Analysis of 187 Publications on Hardware Reverse Engineering (Ruhr U., MPI)
By Technical Paper Link - 27 Mar, 2026 - Comments: 0

A new technical paper, "SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research," was published by the Ruhr University Bochum and the Max Planck Institute for Security and Privacy. Abstract "As hardware serves as the root of trust in modern computing systems, Hardware Reverse Engineering (HRE) is foundational for security assurance. In practice, HRE en... » read more

Systematic Analysis of CPU-Induced Slowdowns in Multi-GPU LLM Inference (Georgia Tech)
By Technical Paper Link - 27 Mar, 2026 - Comments: 0

A new technical paper, "Characterizing CPU-Induced Slowdowns in Multi-GPU LLM Inference," was published by the Georgia Institute of Technology. Abstract "Large-scale machine learning workloads increasingly rely on multi-GPU systems, yet their performance is often limited by an overlooked component: the CPU. Through a detailed study of modern large language model (LLM) inference and servin... » read more

How SW and HW Vulnerabilities Can Complement LLM-Specific Algorithmic Attacks (UT Austin, Intel et al.)
By Technical Paper Link - 20 Mar, 2026 - Comments: 0

A new technical paper, "Cascade: Composing Software-Hardware Attack Gadgets for Adversarial Threat Amplification in Compound AI Systems," was published by the University of Texas, Austin, Intel Labs, Symmetry Systems, Microsoft and Georgia Tech. Abstract "Rapid progress in generative AI has given rise to Compound AI systems - pipelines comprised of multiple large language models (LLM), so... » read more

Bias- and Temperature-Dependent Noise Measurements to Investigate Carrier Transport at the Tellurium Interface (POSTECH)
By Technical Paper Link - 20 Mar, 2026 - Comments: 0

A new technical paper, "Revealing and Engineering Contact-Origin Noise in Ultrathin Tellurium Transistors," was published by researchers at Pohang University of Science and Technology. Abstract "Tellurium (Te) has emerged as a promising p-type semiconductor for ultrathin electronics owing to its strong air stability, excellent hole transport, narrow bandgap, and BEOL-integration compatibi... » read more

Replay‑based Validation as a Scalable Methodology for Chiplet‑based Systems (Intel, Synopsys)
By Technical Paper Link - 18 Mar, 2026 - Comments: 0

A new technical paper, "ODIN-Based CPU-GPU Architecture with Replay-Driven Simulation and Emulation," was published by researchers at Intel, Nvidia and Synopsys. Abstract "Integration of CPU and GPU technologies is a key enabler for modern AI and graphics workloads, combining control-oriented processing with massive parallel compute capability. As systems evolve toward chiplet-based archite... » read more

Identifying Read Disturbance Threshold of DRAM Chips (ETH Zurich, Rutgers)
By Technical Paper Link - 17 Mar, 2026 - Comments: 0

A new technical paper, "DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips," was published by ETH Zurich and Rutgers University. Abstract "State-of-the-art DRAM read disturbance mitigations rely on the read disturbance threshold (RDT) (e.g., the number of aggressor row activations needed to induce the first read disturba... » read more

Analysis of the Evolving Landscape of Ultra-low-power Edge AI Processors (U. of Austria, ETH Zurich)
By Technical Paper Link - 17 Mar, 2026 - Comments: 0

A new technical paper, "Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review," was published by University of Austria and ETH Zurich. Abstract "This review examines the rapidly evolving landscape of ultra-low-power edge processors, covering heterogeneous Systems-on-Chips (SoCs), neural accelerators, near-sensor and in-sensor architectures, and emerging dataflow a... » read more

Optimizing Oxide Interfaces To Preserve Device Performance in TMDC-based Transistors (imec, ETH Zurich)
By Technical Paper Link - 17 Mar, 2026 - Comments: 0

A new technical paper, "Oxide induced degradation in MoS2 field-effect transistors," was published by researchers at imec and ETH Zurich. Abstract excerpt "Transition Metal Dichalcogenides (TMDC) are promising candidates for future scaled transistor channels but their performance is often degraded by imperfections such as the interface with amorphous gate oxides. This study examines how amo... » read more

3D DRAM with CBA Technology (Georgia Tech)
By Technical Paper Link - 16 Mar, 2026 - Comments: 0

A new technical paper, "System-Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM Architectures," was published by researchers at Georgia Tech. Abstract "3D DRAM has emerged as a promising approach for continued density scaling, but its viability is limited by routing and hybrid bonding constraints to periphery, which may degrade sensing margin, laten... » read more

Systematic Training and Validation of AI-based Systems With Digital Twins and Scenario Engineering
By Technical Paper Link - 16 Mar, 2026 - Comments: 0

A new technical paper, "Towards Structured Training and Validation of AI-based Systems with Digital Twin Scenarios," was published by researchers at RWTH Aachen University and RIF e.V. Abstract "Artificial intelligence (AI) has emerged as a pivotal technology for autonomous systems across various domains, but quality assurance remains challenging due to limited training data and inadequate ... » read more

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