Author's Latest Posts


Wafer-on-Wafer Hybrid Bonding: Reticle Placements To Achieve Efficient NW Topologies (ETH Zurich)


Researchers from ETH Zurich published the new technical paper "Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding." Abstract "Transformer-based large language models are increasingly constrained by data movement as communication bandwidth drops sharply beyond the chip boundary. Wafer-scale integration using wafer-on-wafer hybrid bonding alleviates this limitation by p... » read more

A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL)


A new technical paper, "NL2GDS: LLM-aided interface for Open Source Chip Design," was published by researchers at University of Bristol and Rutherford Appleton Laboratory. Abstract "The growing complexity of hardware design and the widening gap between high-level specifications and register-transfer level (RTL) implementation hinder rapid prototyping and system design. We introduce NL2GDS (... » read more

Unified, Traceable Framework For Risk Assessment in Automotive Semiconductors (Robert Bosch)


A new technical paper, "An Integrated Failure and Threat Mode and Effect Analysis (FTMEA) Framework with Quantified Cross-Domain Correlation Factors for Automotive Semiconductors," was published by researchers at Robert Bosch GmbH. Abstract "The automotive industry faces increasing challenges in ensuring both functional safety (FuSa) and cybersecurity for complex semiconductor devices. Tr... » read more

10-Year Roadmap for AI + Hardware (UIUC, UCLA, Stanford et al.)


Researchers from University of Illinois Urbana-Champaign, UCLA, Stanford University, Nvidia, Google, et al. have released “AI+HW 2035: Shaping the Next Decade”. Abstract “Artificial intelligence (AI) and hardware (HW) are advancing at unprecedented rates, yet their trajectories have become inseparably intertwined. The global research community lacks a cohesive, long-term vision t... » read more

Optimizing In-Memory AI Accelerators Across Multiple Workloads (KAUST, Compumacy)


Researchers from KAUST and Compumacy for Artificial Intelligence Solutions have released “Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators”. Abstract “Software-hardware co-design is essential for optimizing in-memory computing (IMC) hardware accelerators for neural networks. However, most existing optimization frameworks target a single workload, lea... » read more

RPU: A Chiplet-Based Architecture To Address The Challenges of the Modern Memory Wall (Harvard University)


Researchers from Harvard University have released “RPU -- A Reasoning Processing Unit”. Abstract “Large language model (LLM) inference performance is increasingly bottlenecked by the memory wall. While GPUs continue to scale raw compute throughput, they struggle to deliver scalable performance for memory bandwidth bound workloads. This challenge is amplified by emerging reasonin... » read more

5 Systems-Level Attack Surfaces That Are Architectural Consequences of Edge-Local Deployment (Imperial College London)


Researchers from Imperial College London and Bytedance released “Systems-Level Attack Surface of Edge Agent Deployments on IoT”. Abstract “Edge deployment of LLM agents on IoT hardware introduces attack surfaces absent from cloud-hosted orchestration. We present an empirical security analysis of three architectures (cloud-hosted, edge-local swarm, and hybrid) using a multi-devic... » read more

Oxide-Semiconductors For Gain Cell Memory Applications (SNU, KAIST)


Researchers from Seoul National University and KAIST published “Oxide Semiconductor Gain Cell-Embedded Memory: Materials and Integration Strategies for Next Generation On-Chip Memory”. Abstract “The data processing demands of the digital era have exposed limitations in conventional memory architectures. Gain cell-embedded dynamic random-access memory based on oxide semiconductor... » read more

Extending Formal Verification to Sequential Circuits (U. of Bremen)


Researchers from University of Bremen have released “Linear Formal Verification of Sequential Circuits using Weighted-AIGs”. Abstract "Ensuring the functional correctness of a digital system is achievable through formal verification. Despite the increased complexity of modern systems, formal verification still needs to be done in a reasonable time. Hence, Polynomial Formal Verifica... » read more

Optimal Heterogeneous Memory Configs for AI Tasks Under Specified Performance Metrics (Stanford, UCSC)


Researchers from Stanford University and University of California, Santa Cruz have released “Heterogeneous Memory Design Exploration for AI Accelerators with a Gain Cell Memory Compiler”. Abstract “As memory increasingly dominates system cost and energy, heterogeneous on-chip memory systems that combine technologies with complementary characteristics are becoming essential. Gain ... » read more

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