Author's Latest Posts


Bias- and Temperature-Dependent Noise Measurements to Investigate Carrier Transport at the Tellurium Interface (POSTECH)


A new technical paper, "Revealing and Engineering Contact-Origin Noise in Ultrathin Tellurium Transistors," was published by researchers at Pohang University of Science and Technology. Abstract "Tellurium (Te) has emerged as a promising p-type semiconductor for ultrathin electronics owing to its strong air stability, excellent hole transport, narrow bandgap, and BEOL-integration compatibi... » read more

Replay‑based Validation as a Scalable Methodology for Chiplet‑based Systems (Intel, Synopsys)


A new technical paper, "ODIN-Based CPU-GPU Architecture with Replay-Driven Simulation and Emulation," was published by researchers at Intel, Nvidia and Synopsys. Abstract "Integration of CPU and GPU technologies is a key enabler for modern AI and graphics workloads, combining control-oriented processing with massive parallel compute capability. As systems evolve toward chiplet-based archite... » read more

Identifying Read Disturbance Threshold of DRAM Chips (ETH Zurich, Rutgers)


A new technical paper, "DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips," was published by ETH Zurich and Rutgers University. Abstract "State-of-the-art DRAM read disturbance mitigations rely on the read disturbance threshold (RDT) (e.g., the number of aggressor row activations needed to induce the first read disturba... » read more

Analysis of the Evolving Landscape of Ultra-low-power Edge AI Processors (U. of Austria, ETH Zurich)


A new technical paper, "Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review," was published by University of Austria and ETH Zurich. Abstract "This review examines the rapidly evolving landscape of ultra-low-power edge processors, covering heterogeneous Systems-on-Chips (SoCs), neural accelerators, near-sensor and in-sensor architectures, and emerging dataflow a... » read more

Optimizing Oxide Interfaces To Preserve Device Performance in TMDC-based Transistors (imec, ETH Zurich)


A new technical paper, "Oxide induced degradation in MoS2 field-effect transistors," was published by researchers at imec and ETH Zurich. Abstract excerpt "Transition Metal Dichalcogenides (TMDC) are promising candidates for future scaled transistor channels but their performance is often degraded by imperfections such as the interface with amorphous gate oxides. This study examines how amo... » read more

3D DRAM with CBA Technology (Georgia Tech)


A new technical paper, "System-Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM Architectures," was published by researchers at Georgia Tech. Abstract "3D DRAM has emerged as a promising approach for continued density scaling, but its viability is limited by routing and hybrid bonding constraints to periphery, which may degrade sensing margin, laten... » read more

Systematic Training and Validation of AI-based Systems With Digital Twins and Scenario Engineering


A new technical paper, "Towards Structured Training and Validation of AI-based Systems with Digital Twin Scenarios," was published by researchers at RWTH Aachen University and RIF e.V. Abstract "Artificial intelligence (AI) has emerged as a pivotal technology for autonomous systems across various domains, but quality assurance remains challenging due to limited training data and inadequate ... » read more

Pathfinding Method That Models ECC Overhead for Chiplet Interconnects (UCLA)


A new technical paper, "Link Quality Aware Pathfinding for Chiplet Interconnects," was published by researchers at UCLA. Abstract "As chiplet-based integration advances, designers must select among short-reach die-to-die interconnect technologies with widely varying shoreline and areal bandwidth density, energy per bit, reach, and raw bit error rate (BER). Meeting stringent delivered BER ... » read more

Neuromorphic Computing Platform In Perovskite Nickelates (UCSD, Rutgers)


A new technical paper, "Protonic nickelate device networks for spatiotemporal neuromorphic computing," was published by researcher at UCSD and Rutgers University. Abstract "Computation in biological neural circuits arises from the interplay of nonlinear temporal responses and spatially distributed dynamic network interactions. Replicating this richness in hardware has remained challenging... » read more

FeFETs With Laminated Gate Stacks For Radiation Resilience in Vertical NAND (Georgia Tech)


A new technical paper, "Enabling Radiation Hardness in Solid-State NAND Storage Utilizing a Laminated Ferroelectric Stack," was published by researchers at Georgia Tech. Abstract "NAND flash forms the core of modern solid-state storage, which is critical for data-intensive AI applications, yet charge-trap NAND suffers rapid threshold-voltage (Vth) degradation under ionizing radiation, causi... » read more

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