Author's Latest Posts


Electrical Model of the Bitflip in SRAM Under Laser Illumination Simulating Laser Fault Injection


A new technical paper, "Electrical modelisation of a bitflip in SRAM cell memory induced by laser fault injection," was published by researchers at Univ Rennes, CNRS, IETR. Abstract "An electrical model of the bitflip in SRAM under laser illumination simulating laser fault injection is proposed. This model is based on a bipolar phototransistor responsible of the amplified induced photocur... » read more

Nanoscale MoS₂-based Memristors Integrated into CMOS Microchips


A new technical paper, "Integration of Low-Voltage Nanoscale MoS2 Memristors on CMOS Microchips" was published by RWTH Aachen and Forschungszentrum Jülich GmbH. Abstract "2D materials (2DMs) are gaining increased attention for applications such as advanced electronics and neuromorphic computing due to their excellent electrical properties. Among these 2DMs, molybdenum disulfide (MoS2) ha... » read more

Router-in-a-Package Design Combining HBM4, Chiplets and In-Package Optics (Technion, Berkeley, UCSD)


A new technical paper "Scaling Routers with In-Package Optics and High-Bandwidth Memories" was posted by researchers at Technion, UC Berkeley and UC San Diego. Abstract "This paper aims to apply two major scaling transformations from the computing packaging industry to internet routers: the heterogeneous integration of high-bandwidth memories (HBMs) and chiplets, as well as in-package optic... » read more

Detecting Architectural Vulnerabilities in Closed-Source RISC-V CPUs (CISPA)


The paper "RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs" was published by researchers at CISPA Helmholtz Center for Information Security. Abstract "The open and extensible RISC-V instruction set has enabled many new CPU vendors and implementations, but most commercial CPUs are closed-source, significantly hindering vul... » read more

New Class Of Semiconductors Made Of Germanium-Tin Alloy (University of Edinburgh et al.)


A new technical paper "High Pressure and Compositionally Directed Route to a Hexagonal GeSn Alloy Class" was published by researchers at the University of Edinburgh, GFZ Helmholtz Centre for Geosciences, the University of Lille, Grenoble Alpes University, the University of Bayreuth and the European Synchrotron facility. Abstract "Despite their electronic dominance, cubic diamond structure... » read more

Less Power and Higher Performance With A Nanolaser With Extreme Dielectric Confinement (DTU)


A new technical paper titled "A nanolaser with extreme dielectric confinement" was published by researchers at Technical University of Denmark (DTU). Abstract "The interaction between light and matter can be enhanced by spatially concentrating the light field and extending photon dwell time. Plasmonic structures can provide strong light confinement but suffer from ohmic losses. Recent adv... » read more

Carrier Mapping in Sub-2nm Node NSFETs with SSRM (imec, KU Leuven)


Researchers from imec and KU Leuven published "Carrier Mapping in Sub-2nm Node Nanosheet Transistors with Scanning Spreading Resistance Microscopy." Abstract "As the semiconductor industry transitions to gate-all-around architectures such as Nanosheet-FETs (NSFETs) for the 2nm node and beyond, controlling parasitic resistance through precise junction engineering is fundamental. This requi... » read more

LLM-Based Learning Platform For Chip Design Education (RPTU)


RPTU University of Kaiserslautern-Landau researchers published "From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs." Abstract "This paper presents an LLM-based learning platform for chip design education, aiming to make chip design accessible to beginners without overwhelming them with technical complexity. It represents the first educational platform... » read more

Automated MLIR-based HLS framework That Generates FPGA HW Designs From A Variety of CNN Layers (TU Dresden)


TU Dresden researchers published "MING: An Automated CNN-to-Edge MLIR HLS framework." Abstract "Driven by the increasing demand for low-latency and real-time processing, machine learning applications are steadily migrating toward edge computing platforms, where Field-Programmable Gate Arrays (FPGAs) are widely adopted for their energy efficiency compared to CPUs and GPUs. To generate high... » read more

CNT Nano Sandpaper For Atomic-Level Polishing (KAIST)


KAIST researchers published "Carbon nanotube sandpaper for atomic-precision surface finishing." Abstract "Sandpapers, also known as coated abrasives, have served as the most familiar surface finishing tools since their first invention in the 13th century. However, they remain unsuitable for advanced industries requiring nanometer-level precision due to limitations in abrasive uniformity a... » read more

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