A new technical paper, “3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography,” was published by researchers at Cornell University, ASM and TSMC.
Abstract
“Next-generation semiconductor devices are adopting three-dimensional (3D) architectures with feature sizes in the few-nanometer regime, creating a need for atomic-scale metrology to identify and resolve performance-limiting fabrication challenges. X-ray methods provide 3D information but lack atomic resolution, while conventional electron microscopy offers limited depth sensitivity. Here we show how multislice electron ptychography, a computational microscopy technique with sub-Ångström lateral and nanometer-scale depth resolution, enables 3D imaging of buried device structures. We image prototype gate-all-around transistors and directly quantify roughness, strain, and defects at the interface of the 3D gate oxide wrapped around the channel. We find that silicon in the 5-nm-thick channel relaxes away from the interfaces, leaving only ~60% of atoms in a bulk-like structure. From a single dataset, ptychography provides quantitative metrology of atomic-scale interface roughness in 3D, previously accessible only through indirect inference, along with strain and other structural parameters needed for device modeling and process development.”
Find the technical paper here. February 2026. Note, this is an unedited version of this manuscript to give early access to its findings.
Karapetyan, S., Zeltmann, S.E., Wilk, G. et al. 3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography. Nat Commun (2026). https://doi.org/10.1038/s41467-026-69733-1. Creative Commons license.
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