Advanced Metrology for Backside Metallization Using Picosecond Laser Ultrasonics


Picosecond Ultrasonics (PULSE) Technology has emerged as a leading metrology solution for characterizing single-layer and multilayer metal films in advanced semiconductor manufacturing [1]. As a non-contact, non-destructive technique, PULSE Technology has become the tool-of-record across multiple device segments, including logic, radio frequency (RF), memory, microelectromechanical systems (MEM... » read more

3D Atomic-Scale Metrology of Strain Relaxation And Roughness in GAAFETs Via Electron Ptychography (Cornell, ASM, TSMC)


A new technical paper, "3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography," was published by researchers at Cornell University, ASM and TSMC. Abstract "Next-generation semiconductor devices are adopting three-dimensional (3D) architectures with feature sizes in the few-nanometer regime, creating a need for atomic-scale me... » read more

The Surface Metrology Decision Guide


The Surface Metrology Decision Guide empowers readers to choose techniques and confidently engage with equipment providers. What’s inside: A side-by-side comparison of the resolution, strengths, and limitations of common surface metrology techniques An in-depth look at advances in and practical considerations for white-light interferometry (WLI) Summary chart of WLI objectives, ma... » read more

Surface Metrology for Hybrid Bonding in Advanced Semiconductor Packaging


Achieving a reliable hybrid bond requires both surfaces to be pristine. To support this requirement, metrology methods such as atomic force microscopy (AFM) and atomic force profilometry (AFP) are critical for surface characterization and process optimization. AFM delivers localized, high-resolution surface measurements, while AFP provides complementary large-area topography scans that ... » read more

Enhancing CMP Process Control with Intelligent Line Monitoring & Integrated Metrology


New logic transistor designs, 3D NAND stacking, and DRAM integration introduce more CMP layers and tighter process windows. Traditional metrology approaches struggle to keep pace, especially with the need for high sampling rates, multiple control zones, and improved signal-to-noise ratios. Onto Innovation’s Intelligent Line Monitoring & Control with Integrated Metrology offers a new appro... » read more

Metrology’s Growing Role In Reducing False Defects


When a good die fails test and gets scrapped, often no one notices, because false failures look identical to real ones. Yet across the industry, these phantom defects are quietly eroding yield, inflating test costs, and masking the true health of manufacturing processes. At advanced nodes and in heterogeneous packaging, where margins are already razor-thin, even minor variations in contact r... » read more

Semiconductor Metrology: IMMSE For The Rapid ID of Defective Chips (Samsung)


A new technical paper titled "Ultra-wide-field imaging Mueller matrix spectroscopic ellipsometry for semiconductor metrology" was published by researchers at Samsung. Abstract "We propose an ultra-wide-field imaging Mueller matrix spectroscopic ellipsometry (IMMSE) system for semiconductor metrology. The IMMSE system achieves large-area measurements with a 20 mm × 20 mm field of ... » read more

CDI For The Metrology Of Copper Pads Used In Hybrid Bonding (Paul Scherrer Institute, Samsung)


A new technical paper titled "Coherent diffractive imaging simulations for wafer inspection of periodic structures" was published by researchers at the Paul Scherrer Institute and Samsung. Excerpt "We present a study of phase retrieval algorithms applied to the metrology of copper pad topography for hybrid bonding. We demonstrate that by including a priori information in the update functi... » read more

Three Methods For Improving Planarization For Diverse Layouts In Advanced Nodes (Fraunhofer IPMS)


A new technical paper titled "Reduced Topography After Stop on Nitride (SON) STI CMP Through Improved Post-Bulk Planarity for Diverse Layouts in Advanced Nodes" was published by researchers at Fraunhofer IPMS. Abstract "Three methods for improving planarization in a ceria free, two step STI CMP process were investigated using patterned test wafers representing 2X nm technology. It was found... » read more

GAA Transistors: 3D Atomic-Scale Metrology of Strain Relaxation and Roughness via Electron Ptychography (Cornell, ASM, TSMC)


A new technical paper titled "3D Atomic-Scale Metrology of Strain Relaxation and Roughness in Gate-All-Around (GAA) Transistors via Electron Ptychography" was published by researchers at Cornell University, ASM and TSMC. Abstract "To improve transistor density and electronic performance, next-generation semiconductor devices are adopting three-dimensional architectures and feature sizes dow... » read more

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