tag: GAAFETs

Scaling Nanoribbon Transistors with Monolayer TMDs (Stanford, Chalmers, Horiba, SLAC)
By Technical Paper Link - 03 Jun, 2026 - Comments: 0

Researchers from Stanford University, Chalmers University of Technology, HORIBA Scientific, and SLAC National Accelerator Laboratory have published “Scaling nanoribbon transistors with monolayer transition metal dichalcogenides”. Abstract “Nanoscale transistors demand aggressive scaling of all channel dimensions—length, width and thickness. Two-dimensional semiconductors (2DS... » read more

ANN Framework for Thermal-Aware Modeling of GAAFETs (NYCU)
By Technical Paper Link - 12 May, 2026 - Comments: 0

A new technical paper, "A Device-Physics-Informed Artificial Neural Network Approach for Thermal-Aware I-V and C-V Modeling of GAA FETs," was published by researchers at National Yang Ming Chiao Tung University. Abstract "This work introduces a device-physics-informed neural network framework for simultaneous modeling of thermal-aware I-V and C-V characteristics of gate-all-around (GAA) f... » read more

Understanding Why Drain-Current in GAAFETs Deviates from Thermionic Dependence at Negative Gate Voltages (Sandia National Lab, LIST)
By Technical Paper Link - 05 May, 2026 - Comments: 0

A new technical paper, "Gate-Drain Leakage Enhanced by Drain-Induced Dielectric Barrier Lowering in Gate-All-Around Field Effect Transistors," was published by researchers at Sandia National Laboratories and Luxembourg Institute of Science and Technology. Abstract "Gate-All-Around Field-Effect Transistors (GAAFETs), now entering high-volume production as successors to fin field-effect tra... » read more

3D Atomic-Scale Metrology of Strain Relaxation And Roughness in GAAFETs Via Electron Ptychography (Cornell, ASM, TSMC)
By Technical Paper Link - 23 Feb, 2026 - Comments: 0

A new technical paper, "3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography," was published by researchers at Cornell University, ASM and TSMC. Abstract "Next-generation semiconductor devices are adopting three-dimensional (3D) architectures with feature sizes in the few-nanometer regime, creating a need for atomic-scale me... » read more

Carrier Mapping in Sub-2nm Node NSFETs with SSRM (imec, KU Leuven)
By Technical Paper Link - 15 Feb, 2026 - Comments: 0

Researchers from imec and KU Leuven published "Carrier Mapping in Sub-2nm Node Nanosheet Transistors with Scanning Spreading Resistance Microscopy." Abstract "As the semiconductor industry transitions to gate-all-around architectures such as Nanosheet-FETs (NSFETs) for the 2nm node and beyond, controlling parasitic resistance through precise junction engineering is fundamental. This requi... » read more

Channel-Last GAA NS Oxide FET (Stanford, TSMC, ETH Zurich et al.)
By Technical Paper Link - 03 Jan, 2026 - Comments: 0

A new technical paper titled "Channel-last gate-all-around nanosheet oxide semiconductor transistors" was published by researchers at Stanford University, TSMC, ETH Zurich, SLAC National Accelerator Laboratory, and Polish Academy of Sciences. Abstract "As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the t... » read more

GAA Transistors: 3D Atomic-Scale Metrology of Strain Relaxation and Roughness via Electron Ptychography (Cornell, ASM, TSMC)
By Technical Paper Link - 14 Jul, 2025 - Comments: 0

A new technical paper titled "3D Atomic-Scale Metrology of Strain Relaxation and Roughness in Gate-All-Around (GAA) Transistors via Electron Ptychography" was published by researchers at Cornell University, ASM and TSMC. Abstract "To improve transistor density and electronic performance, next-generation semiconductor devices are adopting three-dimensional architectures and feature sizes dow... » read more

Device Architecture For 2D Material-Based mNS-FETs In Sub-1nm Nodes (Sungkyunkwan Univ., Alsemy)
By Technical Paper Link - 24 Jun, 2025 - Comments: 0

A new technical paper titled "Exploring optimal TMDC multi-channel GAA-FET architectures at sub-1nm nodes" was published by researchers at Sungkyunkwan University and Alsemy Inc. "This paper explores the design and optimization of multi-Nanosheet Field-Effect Transistors (mNS-FETs) employing a Transition Metal Dichalcogenide (TMDC) channel, specifically MoS2, for the 0.7 nm technology node u... » read more

Electrical Properties of ML and BL MoS2 GAA NS FETs With Source/Drain Metal Contacts (NYCU)
By Technical Paper Link - 31 May, 2025 - Comments: 0

A new technical paper titled "Electrical Characteristics of ML and BL MoS2 GAA NS FETs With Source/Drain Metal Contacts" was published by researchers at National Yang Ming Chiao Tung University. Abstract "This paper reports source/drain (S/D) contact issues in monolayer and bilayer (BL) MoS2 devices through density-functional-theory (DFT) calculation and device simulation. We begin by ana... » read more

Demonstration Of An ALD IWO Channel In A GAA Nanosheet FET Structure (Georgia Tech, Micron)
By Technical Paper Link - 14 Feb, 2025 - Comments: 0

A new technical paper titled "First Demonstration of High-Performance and Extremely Stable W-Doped In2O3  Gate-All-Around (GAA) Nanosheet FET" was published by researchers at Georgia Institute of Technology and Micron. Abstract "We demonstrate a gate-all-around (GAA) nanosheet FET featuring an atomic layer-deposited (ALD) tungsten (W)-doped indium oxide (In2O3), or indium tungsten oxide ... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy