Author's Latest Posts


Speeding-Up Thermal Simulations Of Chips With ML


A new technical paper titled "A Thermal Machine Learning Solver For Chip Simulation" was published by researchers at Ansys. Abstract "Thermal analysis provides deeper insights into electronic chips' behavior under different temperature scenarios and enables faster design exploration. However, obtaining detailed and accurate thermal profile on chip is very time-consuming using FEM or CFD. Th... » read more

Adaptive Memristive Hardware


A new technical paper titled "Self-organization of an inhomogeneous memristive hardware for sequence learning" was just published by researchers at University of Zurich, ETH Zurich, Université Grenoble Alpes, CEA, Leti and Toshiba. "We design and experimentally demonstrate an adaptive hardware architecture Memristive Self-organizing Spiking Recurrent Neural Network (MEMSORN). MEMSORN incorp... » read more

Six Qubit Processor (TU Delft, QuTech, TNO)


A new technical paper titled "Universal control of a six-qubit quantum processor in silicon" was just published by researchers at Delft University of Technology, QuTech and Netherlands Organization for Applied Scientific Research (TNO). "We increase the number of qubits and simultaneously achieve respectable fidelities for universal operation, state preparation and measurement. We design, fa... » read more

Framework Based on an RISC-V Microprocessor Supporting LiM Operations


A new technical paper titled "RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures" was published by researchers at Politecnico di Torino (Italy), Univerity of Tor Vergata (Italy), and University of Twente (The Netherlands). Abstract: "Most modern CPU architectures are based on the von Neumann principle, where memory and processing units are separate entities. Although processin... » read more

Visual Fault Inspection Using A Hybrid System Of Stacked DNNs


A technical paper titled "Improving automated visual fault inspection for semiconductor manufacturing using a hybrid multistage system of deep neural networks" was published by researchers at Chemnitz University of Technology (Germany). According to the paper, "this contribution introduces a novel hybrid multistage system of stacked deep neural networks (SH-DNN) which allows the localization... » read more

Decreasing Refresh Latency of Off-the-Shelf DRAM Chips


A new technical paper titled "HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips" was published by researchers at ETH Zürich, TOBB University of Economics and Technology and Galicia Supercomputing Center (CESGA). Abstract "DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh oper... » read more

Functional-Engineered MXene Transistors


A new technical paper titled "High-throughput design of functional-engineered MXene transistors with low-resistive contacts" was published by researchers at Indian Institute of Science (IISc) Bangalore. Abstract (partial): "Two-dimensional material-based transistors are being extensively investigated for CMOS (complementary metal oxide semiconductor) technology extension; nevertheless, down... » read more

Cybersecurity & FPGA Devices


A technical paper titled "A Survey on FPGA Cybersecurity Design Strategies" is presented by researchers at Université Laval, Canada. Abstract (partial): "This paper presents a critical literature review on the security aspects of field programmable gate array (FPGA) devices. FPGA devices present unique challenges to cybersecurity through their reconfigurable nature. This paper also pays sp... » read more

Spin–Orbit Qubit With A Single Hole Electrostatically Confined In A Natural Silicon Metal-Oxide-Semiconductor Device


A new technical paper titled "A single hole spin with enhanced coherence in natural silicon" was published by researchers at Université Grenoble Alpes, CEA, LETI, and CNRS. Abstract: "Semiconductor spin qubits based on spin–orbit states are responsive to electric field excitations, allowing for practical, fast and potentially scalable qubit control. Spin electric susceptibility, however,... » read more

FP8: Cross-Industry Hardware Specification For AI Training And Inference (Arm, Intel, Nvidia)


Arm, Intel, and Nvidia proposed a specification for an 8-bit floating point (FP8) format that could provide a common interchangeable format that works for both AI training and inference and allow AI models to operate and perform consistently across hardware platforms. Find the technical paper titled " FP8 Formats For Deep Learning" here. Published Sept 2022. Abstract: "FP8 is a natural p... » read more

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