Author's Latest Posts

QubiC: An Open-Source FPGA-Based Control and Measurement System for Superconducting Quantum Information Processors
By Technical Paper Link - 09 Mar, 2022 - Comments: 0

Abstract: "As quantum information processors grow in quantum bit (qubit) count and functionality, the control and measurement system becomes a limiting factor to large-scale extensibility. To tackle this challenge and keep pace with rapidly evolving classical control requirements, full control stack access is essential to system-level optimization. We design a modular field-programmable gate a... » read more

Pinpointing the Dominant Component of Contact Resistance to Atomically Thin Semiconductors
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract "Achieving good electrical contacts is one of the major challenges in realizing devices based on atomically thin two-dimensional (2D) semiconductors. Several studies have examined this hurdle, but a universal understanding of the contact resistance and an underlying approach to its reduction are currently lacking. In this work we expose the shortcomings of the classical contact resist... » read more

SparseP: Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Systems
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract "Several manufacturers have already started to commercialize near-bank Processing-In-Memory (PIM) architectures. Near-bank PIM architectures place simple cores close to DRAM banks and can yield significant performance and energy improvements in parallel applications by alleviating data access costs. Real PIM systems can provide high levels of parallelism, large aggregate memory bandwi... » read more

Zero-Bias Power-Detector Circuits based on MoS2 Field-Effect Transistors on Wafer-Scale Flexible Substrates
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract: "We demonstrate the design, fabrication, and characterization of wafer-scale, zero-bias power detectors based on two-dimensional MoS2 field effect transistors (FETs). The MoS2 FETs are fabricated using a wafer-scale process on 8 μm thick polyimide film, which in principle serves as flexible substrate. The performances of two CVD-MoS2 sheets, grown with different processes and showi... » read more

Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract:  "The expansive globalization of the semiconductor supply chain has introduced numerous untrusted entities into different stages of a device’s lifecycle, enabling them to compromise its security. To make matters worse, the increasing complexity in the design as well as aggressive time-to-market requirements of the newer generation of integrated circuits can lead either designers t... » read more

Advances in Logic Locking: Past, Present, and Prospects
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract: "Logic locking is a design concealment mechanism for protecting the IPs integrated into modern System-on-Chip (SoC) architectures from a wide range of hardware security threats at the IC manufacturing supply chain. Logic locking primarily helps the designer to protect the IPs against reverse engineering, IP piracy, overproduction, and unauthorized activation. For more than a decade,... » read more

Rethinking Watermark: Providing Proof of IP Ownership in Modern SoCs
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract "Intellectual property (IP) cores are essential to creating modern system-on-chips (SoCs). Protecting the IPs deployed in modern SoCs has become more difficult as the IP houses have been established across the globe over the past three decades. The threat posed by IP piracy and overuse has been a topic of research for the past decade or so and has led to creation of a field called wat... » read more

Interfacial ferroelectricity in marginally twisted 2D semiconductors
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract "Twisted heterostructures of two-dimensional crystals offer almost unlimited scope for the design of new metamaterials. Here we demonstrate a room temperature ferroelectric semiconductor that is assembled using mono- or few-layer MoS2. These van der Waals heterostructures feature broken inversion symmetry, which, together with the asymmetry of atomic arrangement at the interface of tw... » read more

A Low-Power BLS12-381 Pairing Cryptoprocessor for Internet-of-Things Security Applications
By Technical Paper Link - 21 Feb, 2022 - Comments: 0

Abstract: "We present the first BLS12-381 elliptic-curve pairing cryptoprocessor for Internet-of-Things (IoT) security applications. Efficient finite-field arithmetic and algorithm-architecture co-optimizations together enable two orders of magnitude energy savings. We implement several countermeasures against timing and power side-channel attacks. Our cryptoprocessor is programmable to provid... » read more

The Wiretap Channel for Capacitive PUF-Based Security Enclosures
By Technical Paper Link - 19 Feb, 2022 - Comments: 0

Abstract: "In order to protect devices from physical manipulations, protective security enclosures were developed. However, these battery-backed solutions come with a reduced lifetime, and have to be actively and continuously monitored. In order to overcome these drawbacks, batteryless capacitive enclosures based on Physical Unclonable Functions (PUFs) have been developed that generate a key-e... » read more

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