Author's Latest Posts

Vertically Stacked ZnO/Te CFETs (POSTECH, Mokpo)
By Technical Paper Link - 09 Jun, 2025 - Comments: 0

A new technical paper titled "Demonstration of Vertically Stacked ZnO/Te Complementary Field-Effect Transistor" was published by researchers at POSTECH and Mokpo National University. Abstract "The complementary field-effect transistor (CFET) structure is a highly area-efficient technology. However, their fabrication entails highly complex integration processes using wafer transfer or recr... » read more

Open-Source RISC-V Cores: Analysis Of Scalar and Superscalar Architectures And Out-Of-Order Machines
By Technical Paper Link - 05 Jun, 2025 - Comments: 0

A new technical paper titled "Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution" was published by researchers at ETH Zurich, Università di Bologna and Univ. Grenoble Alpes, Inria. Abstract "Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) throu... » read more

Determinants Of Bond Wave Speed In Wafer Bonding (Yokohama, TEL)
By Technical Paper Link - 05 Jun, 2025 - Comments: 0

A recent technical paper titled "Factors determining bond wave speed in wafer bonding" was published by researcher at Yokohama National University, Tokyo Electron Kyushu Limited and ANVOS Analytics. Abstract "Wafer-level direct bonding has become a critical process for advanced 3D architectures in logic, memory, and CMOS image sensors. The minimization of the wafer distortion caused by wafe... » read more

Hardware-Oriented Analysis of Multi-Head Latent Attention (MLA) in DeepSeek-V3 (KU Leuven)
By Technical Paper Link - 04 Jun, 2025 - Comments: 0

A new technical paper titled "Hardware-Centric Analysis of DeepSeek's Multi-Head Latent Attention" was published by researchers at KU Leuven. Abstract "Multi-Head Latent Attention (MLA), introduced in DeepSeek-V2, improves the efficiency of large language models by projecting query, key, and value tensors into a compact latent space. This architectural change reduces the KV-cache size and s... » read more

Integration of High-Density Polymer Waveguides With Silicon Photonics for CPO (imec, Ghent)
By Technical Paper Link - 03 Jun, 2025 - Comments: 0

A technical paper titled "Low-Loss Integration of High-Density Polymer Waveguides with Silicon Photonics for Co-Packaged Optics" was published by researchers at imec and Ghent University. Abstract "Co-Packaged Optics applications require scalable and high-yield optical interfacing solutions to silicon photonic chiplets, offering low-loss, broadband, and polarization-independent optical coup... » read more

V-NAND PUFs (Seoul National University, SK hynix)
By Technical Paper Link - 03 Jun, 2025 - Comments: 0

A new technical paper titled "Concealable physical unclonable functions using vertical NAND flash memory" was published by researchers at Seoul National University and SK hynix. The paper proposes "a concealable PUF using V-NAND flash memory by generating PUF data through weak Gate-Induced-Drain-Leakage (GIDL) erase." Find the technical paper here. June 2025. Park, SH., Koo, RH., Yang,... » read more

Quantifying The PFAS Impact In ICs Manufacturing (Harvard University)
By Technical Paper Link - 03 Jun, 2025 - Comments: 0

A new technical paper titled "Modeling PFAS in Semiconductor Manufacturing to Quantify Trade-offs in Energy Efficiency and Environmental Impact of Computing Systems" was published by researchers at Harvard University and Mohamed Bin Zayed University of AI (MBZUAI). "The electronics and semiconductor industry is a prominent consumer of per- and poly-fluoroalkyl substances (PFAS), also known a... » read more

Customizing An LLM Tailored Specifically For VHDL Code And Design Of High Performance Processors (IBM)
By Technical Paper Link - 03 Jun, 2025 - Comments: 0

A new technical paper titled "Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors" was published by researchers at IBM. Abstract "The use of Large Language Models (LLMs) in hardware design has taken off in recent years, principally through its incorporation in tools that increase chip designer productivity. There has been considerable discussion about the ... » read more

Arithmetic Intensity In Decoding: A Hardware-Efficient Perspective (Princeton University)
By Technical Paper Link - 03 Jun, 2025 - Comments: 0

A new technical paper titled "Hardware-Efficient Attention for Fast Decoding" was published by researchers at Princeton University. Abstract "LLM decoding is bottlenecked for large batches and long contexts by loading the key-value (KV) cache from high-bandwidth memory, which inflates per-token latency, while the sequential nature of decoding limits parallelism. We analyze the interplay amo... » read more

Roadmap for AI HW Development, With The Role of Photonic Chips In Supporting Future LLMs (CUHK, NUS, UIUC, Berkeley)
By Technical Paper Link - 01 Jun, 2025 - Comments: 0

A new technical paper titled "What Is Next for LLMs? Next-Generation AI Computing Hardware Using Photonic Chips" was published by researchers at The Chinese University of Hong Kong, National University of Singapore, University of Illinois Urbana-Champaign and UC Berkeley. Abstract "Large language models (LLMs) are rapidly pushing the limits of contemporary computing hardware. For example, t... » read more

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