Author's Latest Posts

SRAM Cell Scaling With Monolithic 3D Integration Of 2D FETs (Penn State)
By Technical Paper Link - 01 Jun, 2025 - Comments: 0

A new technical paper titled "Enabling static random-access memory cell scaling with monolithic 3D integration of 2D field-effect transistors" was published by researchers at The Pennsylvania State University. Abstract "Static Random-Access Memory (SRAM) cells are fundamental in computer architecture, serving crucial roles in cache memory, buffers, and registers due to their high-speed perf... » read more

Chiplet-to-Chiplet Gateway Architecture, A C2C Interface Bridging Two Chiplet Protocols (Peter Grünberg, Jülich Supercomputing Centre)
By Technical Paper Link - 31 May, 2025 - Comments: 0

A new technical paper titled "Modeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-based Co-Design" was published by researchers at Peter Grünberg Institute and Jülich Supercomputing Centre. Abstract "Chiplet-based processor design, which combines small dies called chiplets to form a larger chip, enables scalable designs at economical costs. This trend has received high attention s... » read more

Offline RL Framework That Dynamically Controls The GPU Clock And Server Fan Speed To Optimize Power Consumption And Computation Time (KAIST)
By Technical Paper Link - 31 May, 2025 - Comments: 0

A new technical paper titled "Power Consumption Optimization of GPU Server With Offline Reinforcement Learning" was published by researchers at Korea Advanced Institute of Science and Technology (KAIST) and KT Research and Development Center. "Optimizing GPU server power consumption is complex due to the interdependence of various components. Conventional methods often involve trade-offs: in... » read more

Electrical Properties of ML and BL MoS2 GAA NS FETs With Source/Drain Metal Contacts (NYCU)
By Technical Paper Link - 31 May, 2025 - Comments: 0

A new technical paper titled "Electrical Characteristics of ML and BL MoS2 GAA NS FETs With Source/Drain Metal Contacts" was published by researchers at National Yang Ming Chiao Tung University. Abstract "This paper reports source/drain (S/D) contact issues in monolayer and bilayer (BL) MoS2 devices through density-functional-theory (DFT) calculation and device simulation. We begin by ana... » read more

A Lightweight Scan Instrumentation For Enhancing The Post-Silicon Test Efficiency in ICs (U. of Florida)
By Technical Paper Link - 31 May, 2025 - Comments: 0

A technical paper titled "Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation" was published by researchers at University of Florida. Abstract "Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-b... » read more

Role of Josephson Junctions In Propelling Quantum Technologies Forward (LBNL, UC Berkeley, et al.)
By Technical Paper Link - 31 May, 2025 - Comments: 0

A new technical paper titled "Josephson Junctions in the Age of Quantum Discovery" was published by researchers at Lawrence Berkeley National Laboratory, UC Berkeley, Gwangju Institute of Science and Technology, Korea University, Max Planck and Anyon Computing. Abstract "The unique combination of energy conservation and nonlinear behavior exhibited by Josephson junctions has driven transfor... » read more

Doping Mechanism Of Pure Nitric Oxide In Tungsten Diselenide Transistors (Purdue, MIT, NYCU)
By Technical Paper Link - 22 May, 2025 - Comments: 0

A technical paper titled "Uncovering the doping mechanism of nitric oxide in high-performance P-type WSe2 transistors" was published by researchers at Purdue University, MIT and National Yang Ming Chiao Tung University (with support from Intel Corporation). "Atomically thin two-dimensional (2D) semiconductors are promising candidates for beyond-silicon electronic devices. However, an excessi... » read more

Optimization Approach For The Dispensing of Thermal Interface Material (KIT, Robert Bosch)
By Technical Paper Link - 21 May, 2025 - Comments: 0

A new technical paper titled "TIMtrace: Coverage Path Planning for Thermal Interface Materials" was published by researchers at Karlsruhe Institute of Technology (KIT) and Robert Bosch GmbH. Abstract "Thermal Interface Materials are used to transfer heat from a semiconductor to a heatsink. They are applied along a dispense path onto the semiconductor and spread over its entire surface once ... » read more

Transformation Of 2D-ICs Into 3D-ICs Using Shuttle Chips From Multi-Project Wafers (Tohoku University)
By Technical Paper Link - 20 May, 2025 - Comments: 0

A new technical paper titled "Die-Level Transformation of 2D Shuttle Chips into 3D-IC for Advanced Rapid Prototyping using Meta Bonding" was published by researchers at Tohoku University. Abstract "Three-dimensional integrated circuit (3D-IC) technology, often referred to as through-silicon via (TSV) formation technology, has been steadily maturing and is increasingly used in advanced semic... » read more

Overview Of 103 Research Papers On Automatic SEM Image Analysis Algorithms For Semiconductor Defect Inspection (KU Leuven, Imec)
By Technical Paper Link - 20 May, 2025 - Comments: 0

A new technical paper titled "Scanning electron microscopy-based automatic defect inspection for semiconductor manufacturing: a systematic review" was published by researchers at KU Leuven and imec. "We identified, categorized, and discussed automatic defect inspection algorithms that analyze scanning electron microscopy (SEM) images for semiconductor manufacturing (SM). This is a topic of c... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy