Author's Latest Posts


Hardware-Based Confidential Computing (NIST)


NIST has published a draft report, titled “Hardware Enabled Security: Hardware-Based Confidential Computing,” which presents an approach for managing machine identities for protection against malware and other security vulnerabilities. Comments are due April 10, 2023. Abstract "Organizations employ a growing volume of machine identities, often numbering in the thousands or millions per ... » read more

SpGEMM Targeting RISC-V Vector Processors (Barcelona Supercomputing Center)


A new technical paper titled "Optimization of SpGEMM with Risc-V vector instructions" was published (preprint) by researchers at the Barcelona Supercomputing Center. Abstract "The Sparse GEneral Matrix-Matrix multiplication (SpGEMM) C=A×B is a fundamental routine extensively used in domains like machine learning or graph analytics. Despite its relevance, the efficient execution of SpGEMM ... » read more

Virtual Process Game To Benchmark Performance of Humans And Computers For Design Of A Semiconductor Fabrication Process


A new technical paper titled "Human–machine collaboration for improving semiconductor process development" was published by researchers at Lam Research. Abstract: "One of the bottlenecks to building semiconductor chips is the increasing cost required to develop chemical plasma processes that form the transistors and memory storage cells These processes are still developed manually using h... » read more

Hardware Virtualization Support in the RISC-V CVA6 Core


A new technical paper titled "CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration" was published (preprint) by researchers at Universidade do Minho, University of Bologna, and ETH Zurich. Abstract "Virtualization is a key technology used in a wide range of applications, from cloud computing to embedded systems. Over the last few years, mainstream comp... » read more

Large Area Synthesis of 2D Material Hexagonal Boron Nitride, Improving Device Characteristics of Graphene


A new technical paper titled "Large-area synthesis and transfer of multilayer hexagonal boron nitride for enhanced graphene device arrays" was published by researchers at Kyushu University, National Institute of Advanced Industrial Science and Technology (AIST), and Osaka University. Abstract "Multilayer hexagonal boron nitride (hBN) can be used to preserve the intrinsic physical properti... » read more

CXL-Based Memory Pooling System Meets Cloud Performance Goals And Significantly Reduces DRAM Cost


A technical paper titled "Pond: CXL-Based Memory Pooling Systems for Cloud Platforms" was published by researchers at Virginia Tech, Intel, Microsoft Azure, Google, and Stone Co. Abstract "Public cloud providers seek to meet stringent performance requirements and low hardware cost. A key driver of performance and cost is main memory. Memory pooling promises to improve DRAM utilization and t... » read more

Printed Electronics: Direct Flipchip Bonding of Ultra-Thin Chip On A Recently-Developed Stretchable Substrate


A new technical paper titled "Flip chip bonding on stretchable printed substrates; the effects of stretchable material and chip encapsulation" was published by researchers at Silicon Austria Labs and Institute for Smart Systems Technologies. Abstract "Stretchable printed electronics have recently opened up new opportunities and applications, including soft robotics, electronic skins, human-... » read more

Using Formal Verification To Optimize HLS-Produced Circuits (ETH Zurich)


A new technical paper titled "Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking" was published by researchers at ETH Zurich. Abstract "Recent HLS efforts explore the generation of dynamically scheduled, dataflow circuits from high-level code; their ability to adapt the schedule at runtime to particular data and control outcomes promises superior performance to standar... » read more

Ternary LIM Operation of the TNAND and TNOR Universal Gates Using DG Feedback FETs


A technical paper titled "Logic-in-Memory Operation of Ternary NAND/NOR Universal Logic Gates using Double-Gated Feedback Field-Effect Transistors" was published by researchers at Korea University. Abstract "In this study, the logic-in-memory operations are demonstrated of ternary NAND and NOR logic gates consisting of double-gated feedback field-effect transistors. The component transistor... » read more

Microarchitectural Side-Channel Attacks And Defenses On Non-Volatile RAM


A new technical paper titled "NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems" was written (preprint) by researchers at UC San Diego, UT Austin, and Purdue University. Abstract "We study microarchitectural side-channel attacks and defenses on non-volatile RAM (NVRAM) DIMMs. In this study, we first perform reverse-engineering of NVRAMs as implemented by the Intel Optane... » read more

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