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Fast Parallel Multi-HDL Compiler (UC Santa Cruz)
By Technical Paper Link - 04 Mar, 2023 - Comments: 0

A technical paper titled "A Multi-threaded Fast Hardware Compiler for HDL" was published by researchers at UC Santa Cruz. Abstract: "A set of new Hardware Description Languages (HDLs) are emerging to ease hardware design. HDL compilation time is a major bottleneck in the designer’s productivity. Moreover, as the HDLs are developed independently, the possibility to share innovations in com... » read more

Energy-Efficient Execution Scheme For Dynamic Neural Networks on Heterogeneous MPSoCs
By Technical Paper Link - 04 Mar, 2023 - Comments: 0

A technical paper titled "Map-and-Conquer: Energy-Efficient Mapping of Dynamic Neural Nets onto Heterogeneous MPSoCs" was published (preprint) by researchers at LAMIH/UMR CNRS, Universite Polytechnique Hauts-de-France and UC Irvine. Abstract "Heterogeneous MPSoCs comprise diverse processing units of varying compute capabilities. To date, the mapping strategies of neural networks (NNs) onto ... » read more

Fabricating Multi-Walled Carbon Nanotubes On Plastic Film
By Technical Paper Link - 04 Mar, 2023 - Comments: 0

A new technical paper titled "Direct formation of carbon nanotube wiring with controlled electrical resistance on plastic films" was published by researchers at Tokyo University of Science. The paper states, "we have developed a simple method to fabricate multi-walled carbon nanotube (MWNT) wiring on a plastic film at room temperature under atmosphere pressure. By irradiating a MWNT thin fil... » read more

Asynchronously Parallel Optimization Method For Sizing Analog Transistors Using Deep Neural Network Learning
By Technical Paper Link - 03 Mar, 2023 - Comments: 0

A new technical paper titled "APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning" was published by researchers at UT Austin and Analog Devices. Abstract "Analog circuit sizing is a high-cost process in terms of the manual effort invested and the computation time spent. With rapidly developing technology and high market demand, bringing automated s... » read more

Agile HW Design: Fully Automatic Equivalence Checking Workflow
By Technical Paper Link - 03 Mar, 2023 - Comments: 0

A new technical paper titled "An Equivalence Checking Framework for Agile Hardware Design" was published by researchers at Portland State University and Intel. Abstract "Agile hardware design enables designers to produce new design iterations efficiently. Equivalence checking is critical in ensuring that a new design iteration conforms to its specification. In this paper, we introduce an eq... » read more

Chiplet Placer with Thermal Consideration for 2.5D ICs
By Technical Paper Link - 27 Feb, 2023 - Comments: 0

A new technical paper titled "Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal Consideration" was published by researchers at National Yang Ming Chiao Tung University (Taiwan). Abstract "This work develops an efficient chiplet placer with thermal consideration for 2.5D ICs. Combining the sequence-pair based tree, branch-and-bound method, and advanced placement/pruning... » read more

Review of Methods to Design Secure Memristor Computing Systems
By Technical Paper Link - 27 Feb, 2023 - Comments: 0

A technical paper titled "Review of security techniques for memristor computing systems" was published by researchers at Israel Institute of Technology, Friedrich Schiller University Jena (Germany), and Leibniz Institute of Photonic Technology (IPHT). Abstract "Neural network (NN) algorithms have become the dominant tool in visual object recognition, natural language processing, and robotic... » read more

Fast Time-Resolved Scanning Tunneling Microscopy (STM) for Nanostructures
By Technical Paper Link - 27 Feb, 2023 - Comments: 0

A new technical paper titled "Externally-triggerable optical pump-probe scanning tunneling microscopy with a time resolution of tens-picosecond" was published by researchers at University of Tsukuba and UNISOKU Co. According to the U. of Tsukaba news article, "OPP STM is an essential method for measuring photo-induced charge carrier dynamics in nanostructures, but requires technical advances... » read more

Security-Aware Compiler-Assisted Countermeasure to Mitigate Fault Attacks on RISC-V
By Technical Paper Link - 26 Feb, 2023 - Comments: 0

A new technical paper titled "CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V" was published by researchers at TU Munich and Fraunhofer Institute for Applied and Integrated Security (AISEC). Abstract "Fault-injection attacks are a risk for any computing system executing security-relevant tasks, such as a secure boot process. While ha... » read more

Index-Based Multi-Core BDD Package With Dynamic Memory Management & Reduced Fragmentation
By Technical Paper Link - 26 Feb, 2023 - Comments: 0

A technical paper titled "EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation" was published by researchers at University of Bremen. ABSTRACT "In recent years, hardware systems have significantly grown in complexity. Due to the increasing complexity, there is a need to continuously improve the quality of the hardware design process. This leads designers t... » read more

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