Author's Latest Posts

Automotive MCUs: Digital Twin of the LBIST Functionality
By Technical Paper Link - 15 Feb, 2023 - Comments: 0

A new technical paper titled "A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin" was written by researchers at Infineon Technologies, University of Bremen, and DFKI GmbH. Abstract "LBIST has been proven to be an effective measure for reaching functional safety goals for automotive microcontrollers. Due to a large variety of recent innovative fea... » read more

Emulation System for Racetrack Memories Based on FPGA
By Technical Paper Link - 13 Feb, 2023 - Comments: 0

A technical paper titled "ERMES: Efficient Racetrack Memory Emulation System based on FPGA" was written by researchers at University of Calabria and TU Dresden. "This paper presents a new emulation system for RTMs based on heterogeneous FPGA-CPU Systems-on-Chips (SoCs). Thanks to its high flexibility, the proposed emulator can be easily configured to evaluate different memory architectures. ... » read more

Advanced Packaging for High-Bandwidth Memory: Influences of TSV size, TSV Aspect Ratio And Annealing Temperature
By Technical Paper Link - 13 Feb, 2023 - Comments: 0

A technical paper titled "Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth Memory Applications" was published by researchers at National Yang Ming Chiao Tung University. Abstract: "The stress of TSV with different dimensions under annealing condition has been investigated. Since the application of TSV and bonding technology has demonstrated a promising approach for ... » read more

ILP-Based Router for Wire-Bonding FBGA Packaging Design
By Technical Paper Link - 13 Feb, 2023 - Comments: 0

A new technical paper titled "ILP-Based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design" was written by researchers at National Taiwan University of Science and Technology. "In this paper, we propose an integer linear programming (ILP)-based router for wire-bonding FBGA packaging design. Our ILP formulation not only can handle design-depende... » read more

Modeling and Thermal Analysis of 3DIC
By Technical Paper Link - 13 Feb, 2023 - Comments: 0

A new technical paper titled "Heat transfer in a multi-layered semiconductor device with spatially-varying thermal contact resistance between layers" was published by researchers at UT Arlington. "This work presents a theoretical model to determine the steady state temperature distribution in a general M-layer structure with spatial variation in thermal contact resistance between adjacent la... » read more

New Method Improves Machine Learning Models’ Reliability, With Less Computing Resources (MIT, U. of Florida, IBM Watson)
By Technical Paper Link - 13 Feb, 2023 - Comments: 0

A new technical paper titled "Post-hoc Uncertainty Learning using a Dirichlet Meta-Model" was published (preprint) by researchers at MIT, University of Florida, and MIT-IBM Watson AI Lab (IBM Research). The work demonstrates how to quantify the level of certainty in its predictions, while using less compute resources. “Uncertainty quantification is essential for both developers and users o... » read more

Nanoscale (5nm) Ferroelectric Semiconductor (University of Michigan)
By Technical Paper Link - 08 Feb, 2023 - Comments: 0

A new technical paper titled "Thickness scaling down to 5 nm of ferroelectric ScAlN on CMOS compatible molybdenum grown by molecular beam epitaxy" was published by researchers at University of Michigan, with DARPA funding. "Ferroelectric semiconductors stand out from others because they can sustain an electrical polarization, like the electric version of magnetism. But unlike a fridge magn... » read more

Hardware Virtualization Support in the RISC-V CVA6 Core
By Technical Paper Link - 08 Feb, 2023 - Comments: 0

A new technical paper titled "CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration" was written by researchers at Universidade do Minho (Portugal), University of Bologna, and ETH Zurich. Abstract Excerpt: "In this article, we describe our work on hardware virtualization support in the RISC-V CVA6 core. Our contribution is multifold and encompasses archite... » read more

Detecting Hardware Trojans In a RISC-V Core’s Post-Layout Phase
By Technical Paper Link - 08 Feb, 2023 - Comments: 0

A new technical paper "Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study" was published by researchers at University of Bremen, DFKI GmbH, and the German Aerospace Center. Abstract: "With the exponential increase in the popularity of the RISC-V ecosystem, the security of this platform must be re-evaluated especially for mission-critical and IoT d... » read more

RSFQ Logic Based Logic Locking Technique For Immunizing Against SAT-Based Attacks
By Technical Paper Link - 08 Feb, 2023 - Comments: 0

A new technical paper titled "C-SAR: SAT Attack Resistant Logic Locking for RSFQ Circuits" was published (preprint) by researchers at University of Southern California. Abstract: "Since the development of semiconductor technologies, exascale computing and its associated applications have required increasing degrees of efficiency. Semiconductor-transistor-based circuits (STbCs) have strugg... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy