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3D Integration And Test Results From TSV-Processed Chips (CERN et al.)
By Technical Paper Link - 20 Jan, 2025 - Comments: 0

A new technical paper titled "3D integration of pixel readout chips using Through-Silicon-Vias" was published by researchers at CERN, IZM Fraunhofer and University of Geneva. Abstract "Particle tracking and imaging detectors are becoming increasingly complex, driven by demands for densely integrated functionality and maximal sensitive area. These challenging requirements can be met using 3D... » read more

Impact of Extremely Low Temperatures On The 5nm SRAM Array Size and Performance
By Technical Paper Link - 20 Jan, 2025 - Comments: 0

A new technical paper titled "Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures" was published by researchers at University of Stuttgart, IIT Kanpur, National Yang Ming Chiao Tung University, Khalifa University, and TU Munich. Abstract "Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temp... » read more

Liquid-Infused Nanostructured Composites As A Universal Thermal Interface Solution for Cooling Applications
By Technical Paper Link - 20 Jan, 2025 - Comments: 0

A new technical paper titled "Liquid-infused nanostructured composite as a high-performance thermal interface material for effective cooling" was published by researchers at Carnegie Mellon University, Oregon State University and Arieca. Abstract "Effective heat dissipation remains a grand challenge for energy-dense devices and systems. As heterogeneous integration becomes increasingly inev... » read more

Vertical AlGaN Heterostructures For Integrated Photonics
By Technical Paper Link - 20 Jan, 2025 - Comments: 0

A new technical paper titled "AlGaN/AlN heterostructures: an emerging platform for integrated photonics" was published by researchers at Humboldt-Universität zu Berlin and Ferdinand-Braun-Institut (FBH). Abstract "We introduce a novel material for integrated photonics and investigate aluminum gallium nitride (AlGaN) on aluminum nitride (AlN) templates as a platform for developing reconfig... » read more

Design-Space Analysis of M3D FPGA With BEOL Configuration Memories (Georgia Tech, UCLA)
By Technical Paper Link - 17 Jan, 2025 - Comments: 0

A new technical paper titled "Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories" was published by researchers at Georgia Tech and UCLA. Abstract "This work presents a novel monolithic 3D (M3D) FPGA architecture that leverages stackable back-end-of-line (BEOL) transistors to implement configuration memory and pass gates, significantly improving area, latency, and power ef... » read more

Loss Processes in Electrochemically Charged Semiconductor Nanocrystal Films (TU Delft)
By Technical Paper Link - 16 Jan, 2025 - Comments: 0

A new technical paper titled "Where Do the Electrons Go? Studying Loss Processes in the Electrochemical Charging of Semiconductor Nanomaterials" was published by researchers at Delft University of Technology. Abstract "Electrochemical charging of films of semiconductor nanocrystals (NCs) allows precise control over their Fermi level and opens up new possibilities for use of semiconductor NC... » read more

Design Space for the Device-Circuit Codesign of NVM-Based CIM Accelerators (TSMC)
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new technical paper/mini-review titled "Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators" was published by researchers at TSMC and National Tsing Hua University. Abstract "Unprecedented penetration of artificial intelligence (AI) algorithms has brought about rapid innovations in electronic hardware, including new memory devi... » read more

Geometric-Aware Model Merging Approach To Enhance Instruction Alignment in Chip LLMs (Nvidia)
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new technical paper titled "ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation" was published by researchers at NVIDIA Research. Abstract: "Recent advancements in large language models (LLMs) have expanded their application across various domains, including chip design, where domain-adapted chip models like ChipNeMo have emerged. However, ... » read more

Domain Wall Fluctuations in Sliding Ferroelectrics (Cambridge, Argonne)
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new technical paper titled "Superconductivity from Domain Wall Fluctuations in Sliding Ferroelectrics" was published by researchers at University of Cambridge and Argonne National Lab. Abstract: "Bilayers of two-dimensional van der Waals materials that lack an inversion center can show a novel form of ferroelectricity, where certain stacking arrangements of the two layers lead to an inter... » read more

Transformation Of Polarons As Tellurene Becomes Thinner
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new research paper titled "Thickness-dependent polaron crossover in tellurene" was published by researchers from Rice University, Lawrence Berkeley National Laboratory, MIT, Argonne National Laboratory, ORNL, Purdue University, and Stanford University. Abstract "Polarons, quasiparticles from electron-phonon coupling, are crucial for material properties including high-temperature supercond... » read more

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