Author's Latest Posts


Novel In-Pixel-in-Memory (P2M) Paradigm for Edge Intelligence (USC)


A new technical paper titled "A processing-in-pixel-in-memory paradigm for resource-constrained TinyML applications" was published by researchers at University of Southern California (USC). According to the paper, "we propose a novel Processing-in-Pixel-in-memory (P2M) paradigm, that customizes the pixel array by adding support for analog multi-channel, multi-bit convolution, batch normaliza... » read more

Training a Quantum Neural Network Requires Only A Small Amount of Data


A new research paper titled "Generalization in quantum machine learning from few training data" was published by researchers at Technical University of Munich, Munich Center for Quantum Science and Technology (MCQST), Caltech, and Los Alamos National Lab. “Many people believe that quantum machine learning will require a lot of data. We have rigorously shown that for many relevant problems,... » read more

Effects of Size Scaling and Device Architecture on the Radiation Response of Nanoscale MOS Transistors


A new technical paper titled "Perspective on radiation effects in nanoscale metal–oxide–semiconductor devices" was published by a researcher at Vanderbilt University, Nashville, Tennessee. The work was partially supported by the Defense Threat Reduction Agency and by the U.S. Air Force Office of Scientific Research and Air Force Research Laboratory. According to the paper, "this Perspect... » read more

State Of The Art And Recent Progress of Reconfigurable Electronic Devices Based on 2D Materials


A new technical paper titled "Emerging reconfigurable electronic devices based on two-dimensional materials: A review" was just published by researchers at TU Dresden, NaMLAb gGmbH, and RWTH Aachen University. Abstract "As the dimensions of the transistor, the key element of silicon technology, are approaching their physical limits, developing semiconductor technology with novel concepts an... » read more

Polynesia, A Novel Hardware/Software Cooperative Design for In-Memory HTAP Databases


A team of researchers from ETH Zurich, Google and Univ. of Illinois Urbana-Champaign recently published a technical paper titled "Polynesia: Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Co-Design". Abstract (partial) "We propose Polynesia, a hardware–software co-designed system for in-memory HTAP [hybrid transactional/anal... » read more

Beyond 5nm: Review of Buried Power Rails & Back-Side Power


A new technical paper titled "A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes" is presented by researchers at UT Austin, Arm Research, and imec. Find the technical paper here. Published July 2022. S. S. T. Nibhanupudi et al., "A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes," in IEEE Transactions... » read more

DNN-Opt, A Novel Deep Neural Network (DNN) Based Black-Box Optimization Framework For Analog Sizing


This technical paper titled "DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks" is co-authored from researchers at The University of Texas at Austin, Intel, University of Glasgow. The paper was a best paper candidate at DAC 2021. "In this paper, we present DNN-Opt, a novel Deep Neural Network (DNN) based black-box optimization framework for analog sizi... » read more

Gemmini: Open-source, Full-Stack DNN Accelerator Generator (DAC Best Paper)


This technical paper titled "Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration" was published jointly by researchers at UC Berkeley and a co-author from MIT.  The research was partially funded by DARPA and won DAC 2021 Best Paper. The paper presents Gemmini, "an open-source, full-stack DNN accelerator generator for DNN workloads, enabling end-to-e... » read more

Advances In Reconfigurable Intelligent Surfaces Hardware Architectures: Beyond 5G/6G


This technical paper titled "Reconfigurable Intelligent Surfaces for Wireless Communications: Overview of Hardware Designs, Channel Models, and Estimation Techniques" is from researchers at IEEE. The paper's abstract states "we overview and taxonomize the latest advances in RIS [reconfigurable intelligent surfaces] hardware architectures as well as the most recent developments in the modelin... » read more

Implementing Cryptographic Algorithms for the RISC-V Instruction Set Architecture in Two Cases


This new technical paper titled "Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms" was published by researchers at Intel, North Arizona University and Google, with partial funding from U.S. Air Force Research Laboratory. Abstract "The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient i... » read more

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