Author's Latest Posts

An Analysis Of Blocking Vs. Non-Blocking Flow Control In On-Chip Networks
By Various Writers - 29 Dec, 2012 - Comments: 0

High end System-on-Chip (SoC) architectures consist of tens of processing engines. These processing engines have varied traffic profiles consisting of priority traffic that require that the latency of the traffic is minimized, controlled bandwidth traffic that require low service jitter on the throughput, and best effort traffic that can tolerate highly variable service. In this paper, we inves... » read more

On-Chip Communications Survey Results
By Various Writers - 19 Dec, 2012 - Comments: 0

This comprehensive report takes a closer look at general technology trends and factors associated with OCCNs, such as core target speeds. It investigates the most popular OCCN topologies being considered for implementation in multi-core SoCs, including networks-on-chip (NoCs), crossbars, peripheral interconnect, and multi-layer bus matrices. It then dives deeper into NoCs, including analyzing a... » read more

Automotive SoC Maker Uses NoC Technology
By Various Writers - 19 Dec, 2012 - Comments: 0

How the world's #1 vision-based Advanced Driver Assistance and Collision Avoidance Systems company uses Arteris FlexNoC interconnect IP to address demanding low-latency requirements in its automotive products. To download this white paper, click here. » read more

Addressing Today’s Complex Clock Modeling Issues With Veloce Emulation Technology
By Various Writers - 19 Dec, 2012 - Comments: 0

Earlier designs were smaller, less complex, and had simpler clocking. A few years back, verification was much easier and clock modeling was not such a big concern. With the drastic increase in the use of System-on-Chip (SoC), designs today are becoming extremely complex with an increasing number of peripherals/external interfaces to consider, requiring a higher numbers of asynchronous clocks. ... » read more

Challenges In Verification Of Clock Domain Crossings
By Various Writers - 19 Dec, 2012 - Comments: 0

Emerging systems have three dimensions of complexity when it comes to making them CDC-safe. First, the number of asynchronous clock domains in designs can range from the tens to the hundreds for complex systems with many components. Second, the master clock frequencies vary per component. It is not uncommon for the ratio between the fastest and the slowest clocks to be greater than 10. Third, t... » read more

TLM-Driven Design And Verification—Time For A Methodology Shift
By Various Writers - 19 Dec, 2012 - Comments: 0

While today’s RTL design and verification flows are a step up from the gate-level flows of two decades ago, RTL flows are straining to meet the demands of most product teams. When designs are sourced and verified at the register transfer level (RTL), IP reuse is difficult, functional verification is lengthy and cumbersome, and architectural decisions cannot be confirmed prior to RTL verificat... » read more

12 Design Techniques For Successful Integration Of Data Converter IP Into An SoC
By Various Writers - 19 Dec, 2012 - Comments: 0

To deliver the demanding performance and faster operation of today’s systems—from communication interfaces to high-image-quality video and multimedia systems—consumer applications employ digital signal processing extensively. Data converters form the interface between the real-world analog signals and the digital domain. They are, therefore, an essential element of the complete signal pro... » read more

Double Patterning From Design Enablement To Verification
By Various Writers - 13 Dec, 2012 - Comments: 0

Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal layers. We discuss the unique design and process characteristics of LELE DP, the challenges they present, and various solutions, including: DP design methodologies, current DP conflict feedback mechanisms, and how they can help designers identify and resolve conflicts. E... » read more

RTL Design-for-Power Methodology
By Various Writers - 06 Dec, 2012 - Comments: 0

This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power. To view this white paper, click here. » read more

Don’t miss Fully-Depleted Tech Symposium during IEDM (SF)
By Various Writers - 04 Dec, 2012 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ If you want to cut through the noise surrounding the choices for 28nm and beyond, an excellent place to start is the SOI Consortium’s Fully Depleted Technology Symposium. As a member of the design and manufacturing communities, this is your chance to see and hear what industry leaders are actually doing. Planar? F... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy