TLM-Driven Design And Verification—Time For A Methodology Shift

While today’s RTL design and verification flows are a step up from the gate-level flows of two decades ago, RTL flows are straining to meet the demands of most product teams. When designs are sourced and verified at the register transfer level (RTL), IP reuse is difficult, functional verification is lengthy and cumbersome, and architectural decisions cannot be confirmed prior to RTL verification. With increasing pressure on today’s SoC and ASIC design teams to deliver more aggressive designs in less time, and the need to get designs right on the first pass, many companies are looking to move to the next level of abstraction beyond RTL to get a much-needed boost in design productivity.

That next level of abstraction is based on transaction level modeling (TLM). By creating TLM IP as their golden source, design teams can ease IP creation and reuse, introduce fewer bugs, spend less time and effort in functional verification, and quickly explore a broad range of micro-architecture implementation options. Design iterations are reduced because TLM verification is much faster than RTL verification, and architectural choices can be verified well before RTL verification. Further, higher-abstraction transaction-level models can be used for hardware/ software co-verification, and can be part of a virtual platform for early software development. The net result of all these advantages will be much higher designer productivity.