Author's Latest Posts

Leveraging Processor Extensibility To Build An Ultra Low-Power Embedded Subsystem
By Various Writers - 07 May, 2014 - Comments: 0

There is increasing demand for electronic devices to execute more functions while consuming less power and silicon area. To achieve this, systems instantiating multiple, heterogeneous processor cores optimized for low power and high performance are gaining popularity among design teams. In these systems, one or more deeply embedded processors execute a limited set of dedicated applications. The... » read more

DPA Countermeasures
By Various Writers - 30 Apr, 2014 - Comments: 0

Smartphones, tablets and other mobile devices con- tain cryptographic keys that protect payments, VPN/network connections and on-device flash memory. Although some smartphones and other devices contain countermeasures, many do not and can be easily compromised. Even a simple radio can tune into the radio frequency emissions from mobile devices and gather side channel information. In some cases,... » read more

Rethinking SoC Verification
By Various Writers - 23 Apr, 2014 - Comments: 1

The introduction of the iPhone in 2007 represented a fundamental shift in electronic system design: moving advanced processing power off of the desktop and into the hands of users everywhere, always. This shift has led to a revolution in mobile—the expansion into the Internet-of-Things, with wearables, connected automobiles and homes. This revolution is causing profound technology challeng... » read more

Hierarchical Timing Analysis: Pros, Cons, And A New Approach
By Various Writers - 23 Apr, 2014 - Comments: 0

As digital semiconductor designs continue to grow larger, designers are looking to hierarchical methodologies to help alleviate huge runtimes. This approach allows designers to select and time certain blocks of logic, generating results more quickly and with fewer memory resources. However, these benefits come at the cost of accuracy. This paper covers the pros and cons of different hierarchica... » read more

How To Improve The Profitability Of Fabless Semiconductor Companies
By Various Writers - 23 Apr, 2014 - Comments: 0

Semiconductor industry gross margins are under pressure. The average gross margin of the industry in Q4 2013 was 53 percent, which was a quarter-over-quarter decline of over 100 basis points (bps), and a continued decline of over 300 bps from the high water mark in Q3 2010 of 56 percent. This white paper explores several effective strategies available to meet the challenges of managing the c... » read more

Localized, System-Level Protocol Checks And Coverage Closure
By Various Writers - 23 Apr, 2014 - Comments: 0

Broadcom recently developed a unified, scalable, verification methodology based on the Veloce emulation platform. In order to test this new environment, they ran a test case, which proved that they can take assertions, compile them into Veloce, and verify that they fire accurately. In so doing, they were able to provide proof of concept for their primary goal: the creation of an internal flow t... » read more

Effectively Manage Material Obsolescence To Avoid Costly Surprises
By Various Writers - 16 Apr, 2014 - Comments: 0

This paper describes the solution that allows complete management and control for companies to optimize their business and their performance on commitment to customers, specifically with respect to effective management of material obsolescence. To view this paper, click here. » read more

DSP-Based Testing
By Various Writers - 16 Apr, 2014 - Comments: 0

ADC and DAC are the most typical mixed signal devices. In mixed signal testing, analog stimulus signal for an ADC is generated by an arbitrary waveform generator (AWG) which employs a D/A converter inside, and an analog signal out of a DAC is measured by a digitizer or a sampler which employs an A/D converter inside. The stimulus signals for these devices are created using mathematical method, ... » read more

Mask Hotspots Are Escaping The Mask Shop
By Various Writers - 16 Apr, 2014 - Comments: 0

Although the overwhelming majority of wafer production issues at the 28nm-and- below process nodes are lithography- and OPC-related, the semiconductor industry is starting to see problems caused by mask hotspots: wafer-level production issues that are caused when the shapes specified by optical proximity correction (OPC) are not faithfully reproduced on the mask. Mask hotspots will account for ... » read more

Advanced Dynamic Power Reduction Techniques
By Various Writers - 09 Apr, 2014 - Comments: 0

Rapid changes in SoC power issues have forced a rethinking of methodologies throughout the design flow to account for power-related effects. At 65 nanometer process nodes and below, leakage power and dynamic power consumption make it increasingly difficult to meet power budgets. Achieving timing and signal integrity closure is now tightly coupled with power optimization and power net distributi... » read more

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