A look at the tradeoffs of various analysis approaches to achieve efficient and accurate timing analysis.
As digital semiconductor designs continue to grow larger, designers are looking to hierarchical methodologies to help alleviate huge runtimes. This approach allows designers to select and time certain blocks of logic, generating results more quickly and with fewer memory resources. However, these benefits come at the cost of accuracy. This paper covers the pros and cons of different hierarchical analysis approaches, as well as options for avoiding the inherent tradeoffs to achieve efficient and accurate timing analysis.
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