Author's Latest Posts

Analog IP Migration Using Design Knowledge Extraction
By Various Writers - 07 Nov, 2013 - Comments: 0

Demonstrated in this paper is a technique for automatic circuit resizing between different technologies. It relies on design knowledge extraction, which renders it very fast compared to full optimization approaches and allows handling of much larger circuits. This technique studies the original design and extracts its major features (basic devices & blocks features, device matching, parasitics,... » read more

Power And Noise Integrity For Analog/Mixed Signal Designs
By Various Writers - 07 Nov, 2013 - Comments: 0

The convergence of advance process technology, increasing levels of integration, and higher operating frequencies pose considerable challenge to IP designers whose circuits are required to function in variety of conditions. Full-custom and mixed signal circuit designers ensure that their circuits will function by simulating for various operating conditions (PVT, input stimuli, etc). One key asp... » read more

CDC Verification Of Billion-Gate SoCs
By Various Writers - 07 Nov, 2013 - Comments: 0

Driven by growing design sizes and complexities and aggressive power requirements, design and verification engineers are witnessing an explosion in the number of asynchronous clocks. Consequently, design and verification teams spend a huge amount of time verifying the correctness of asynchronous boundaries on the chip. The paper describes three methodologies to address this issue and the benefi... » read more

The Internet Of Things Business Index
By Various Writers - 07 Nov, 2013 - Comments: 0

The Internet of Things (IoT) is an idea whose time has finally come. Falling technology costs, developments in complementary fields like mobile and cloud, together with support from governments have all contributed to the dawning of an IoT “quiet revolution”. Now, after more than a decade of slow progress, the business community is beginning to look seriously at the IoT—to the extent that... » read more

Vista Virtual Prototyping
By Various Writers - 24 Oct, 2013 - Comments: 0

Vista Virtual Prototyping provides an early, abstract functional model of the hardware to software engineers even before the hardware design is implemented in RTL. It can run software on embedded processor models at speeds par with board support packages, providing sufficiently fast simulation models for OS and application software validation. The Vista Virtual Prototyping solution has two dist... » read more

CDC Methodology For Fast-To-Slow Clocks
By Various Writers - 24 Oct, 2013 - Comments: 0

CDC checking of any asynchronous clock domain crossing requires that the data path and the control path be identified and that the receive clock domain data flow is controlled by a multiplexer with a select line that is fed by a correctly synchronized control line.  Meridian CDC identifies all the data and associated control paths in a design and will ensure that the control signals passing fr... » read more

A Case Study: How A Call For SOS Improved Designer Productivity
By Various Writers - 24 Oct, 2013 - Comments: 0

Authors: Andrey Medushevskiy, CAD/PDK Manager; Konstantin Bragin, ASIC Verification Lead; Michail Kakoulin, Head IC Design Centre Milandr Moscow, Russia Milandr is a twenty-year-old product company based in Moscow, Russia, that builds high-reliability integrated circuit (IC) products for the aerospace, avionics, automotive, and consumer markets. Their product lines include microcontrollers... » read more

Virtual Prototypes For Early Software Development
By Various Writers - 24 Oct, 2013 - Comments: 0

In previous white papers, we've looked at the demands of the rapidly changing market and how the use of virtual prototypes has evolved to help meet them. In this white paper, we look specifically at the challenges of developing some of the hardware-dependent software layers - namely boot ROM code, OS bring-up, driver development - used in fast-evolving mobile devices and how to use virtual prot... » read more

Improving Design Reliability By Avoiding Electrical Overstress
By Various Writers - 17 Oct, 2013 - Comments: 0

Electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers, and is responsible for the vast majority of device failures and product returns. The use of multiple voltages increases the risk of EOS, so IC designers need to increase their diligence to ensure that thin-oxide digital transistors do not have direct or indirect paths to high-voltage ... » read more

Tackling Verification Challenges With Interconnect Validation Tool
By Various Writers - 17 Oct, 2013 - Comments: 0

An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically, interconnect verification complexity also grows, considering the master/slave numbers, various protocols, different kinds of transactions, and multi-layered t... » read more

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