Complexity involving interconnects is growing as the capacity of SoCs increases, and with that comes a growing verification challenge.
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically, interconnect verification complexity also grows, considering the master/slave numbers, various protocols, different kinds of transactions, and multi-layered topology. The traditional ways of firing many direct tests, or applying a divide-and-conquer strategy, do not provide a holistic verification for SoC interconnects. A systematic approach must be adopted to tackle the challenge and make the process more efficient. In this paper, we discuss how we adopted Cadence Verification IP for AMBA Protocols and Cadence Interconnect Validator, an industry-leading tool for fabric verification. We convey how these tools helped us to improve verification efficiency, and we discuss a verification environment that we created with the Universal Verification Methodology (UVM).
To view this white paper, click here.
30 facilities planned, including 10/7nm processes, but trade war and economic factors could slow progress.
Leaders of three R&D organizations, Imec, Leti and SRC, discuss the latest chip trends in AI, packaging and quantum computing.
Applied Materials’ VP looks at what’s next for semiconductor manufacturing and the impact of variation, new materials and different architectures.
What could make this memory type stand out from the next-gen memory crowd.
Researchers digging into ways around the von Neumann bottleneck.
Semiconductor devices face many hazards before and after manufacturing that can cause them to fail prematurely.
Chips will cost more to design and manufacture even without pushing to the latest node, but that’s not the whole story.
This will go down as a good year for the semiconductor industry, where new markets and innovation were both necessary and rewarded.
Experts at the Table, Part 1: Impact on the supply chain, who’s using advanced packaging, and the cost of packaging versus device scaling.
Companies battle it out to get artificial intelligence to the edge using various chip architectures as their weapons of choice.
Technology adds more granularity, but starting point for design shifts as architectures cope with greater volumes of data.
Bulk CMOS, FD-SOI and finFETs all on tap as big players vie for differentiation. But where will chipmakers go after 28nm?
30 facilities planned, including 10/7nm processes, but trade war and economic factors could slow progress.
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply