Tackling Verification Challenges With Interconnect Validation Tool

Complexity involving interconnects is growing as the capacity of SoCs increases, and with that comes a growing verification challenge.


An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically, interconnect verification complexity also grows, considering the master/slave numbers, various protocols, different kinds of transactions, and multi-layered topology. The traditional ways of firing many direct tests, or applying a divide-and-conquer strategy, do not provide a holistic verification for SoC interconnects. A systematic approach must be adopted to tackle the challenge and make the process more efficient. In this paper, we discuss how we adopted Cadence Verification IP for AMBA Protocols and Cadence Interconnect Validator, an industry-leading tool for fabric verification. We convey how these tools helped us to improve verification efficiency, and we discuss a verification environment that we created with the Universal Verification Methodology (UVM).

To view this white paper, click here.

Leave a Reply

(Note: This name will be displayed publicly)