tag: multi-core

RISC-V Driving New Verification Concepts
By Brian Bailey - 12 Apr, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss gaps in tools and why new methodologies are needed for RISC-V processors, with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, ... » read more

Heterogeneous Multi-Core HW Architectures With Fine-Grained Scheduling of Layer-Fused DNNs
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks" was published by researchers at KU Leuven and TU Munich. Abstract "To keep up with the ever-growing performance demand of neural networks, specialized hardware (HW) accelerators are shifting towards multi-core and chiplet architectures. So far, thes... » read more

Shifting Auto Architectures
By Ed Sperling - 29 Apr, 2021 - Comments: 0

Domain controllers and gateways are being replaced by central processing modules and zonal gateways to handle all of the data traffic in a vehicle. Ron DiGiuseppe, automotive IP segment manager at Synopsys, talks with Semiconductor Engineering about how automotive applications are changing, what that means for engineering teams, and how they will shift as AI is increasingly deployed. » read more

Toward A Lingua Franca For Intelligent System Design
By Frank Schirrmeister - 26 Sep, 2019 - Comments: 1

As the EDA industry is moving up further and further towards the intelligent design of full systems, this year’s Forum on Design Languages (FDL) offered a great update on the status quo with regard to where languages fit into this transition. It looks like the next step will not be one universal language as previously targeted back when there was a flurry of introductions of new programming m... » read more

Improving Simulation Throughput Using The Xcelium Parallel Logic Simulator
By Cadence - 26 Jun, 2019 - Comments: 0

Simulators have been around for a long time. First, there were interpreters in the ‘80s and ‘90s, and despite being relatively slow, they were a big step up from fabricating the design and hoping it worked. However, as designs continued to increase in size, the interpreters could not keep up with simulation needs, and innovation was required for simulators to keep pace with new technology. ... » read more

SLX Multi-Objective Optimization (MOPT)
By Silexica - 24 Apr, 2019 - Comments: 0

Technologies such as autonomous cars and 5G communication are seeing a rapid increase in the number of processing elements (PE) per platform. Where software professionals were used to programming one, two or a handful of cores, the game has now changed. Intel’s Many Integrated Core Architecture [3] contains up to 78 cores, Nvidia Tegra XI[2] has up to 260 cores and Adapteva’s Epiphany-V[1] ... » read more

Big Shift In Multi-Core Design
By Ann Mutschler - 03 Apr, 2019 - Comments: 0

Hardware and software engineers have a long history of working independently of each other, but that insular behavior is changing in emerging areas such as AI, machine learning and automotive as the emphasis shifts to the system level. As these new markets consume more semiconductor content, they are having a big impact on the overall design process. The starting point in many of these desig... » read more

Impacts Of Reliability On Power And Performance
By Ann Mutschler - 13 Dec, 2018 - Comments: 0

Making sure a complex system performs as planned, and providing proper access to memories, requires a series of delicate tradeoffs that often were ignored in the past. But with performance improvements increasingly tied to architectures and microarchitectures, rather than just scaling to the next node, approaches such as determinism and different kinds of caching increasingly are becoming criti... » read more

The Perfect Risk
By Brian Bailey - 27 Sep, 2018 - Comments: 0

The development of semiconductors is an act of risk management. Very simply put, if you take on too much risk, it could lead to product failure or a missed market window, both of which can cost $M. For a company that only produces one or two products a year, that can spell total disaster. If you do not take on enough risk, you are probably not going to end up with a competitive product that ... » read more

Tech Talk: Faster Simulation
By Ann Mutschler - 22 Mar, 2018 - Comments: 0

Cadence’s Adam Sherer talks about how to speed up simulation in complex multi-core designs. https://youtu.be/lDgMwU5KN7U » read more

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