Automated Analog Design Constraint Checking

By Hossam Sarhan and Alexandre Arriordaz

Overview
Analog integrated circuits (ICs) are used to control and regulate conditions such as temperature, speed, sound, and electrical current. In analog ICs, voltage and current vary continuously at specified points in the circuit. One of the biggest challenges in analog integrated circuit (IC) design is to achieve and maintain accurate ratios: capacitor ratio, resistor ratio, current mirror ratio, etc. Analog design circuitry is sensitive to such device ratios, so ensuring these ratios remain consistent from design to implementation, and on through manufacturing and operation, is essential to achieving the expected performance of the circuit and the product lifetime. Replacing tiresome, error-prone manual inspections with automated constraint checking ensures consistent, accurate, and precise identification of even the most subtle layout discrepancies.

Analog circuitry performance and reliability
The performance and reliability of analog designs are closely linked to the layout implementation. There are many different conditions that have a direct impact on an analog design’s reliability, performance, and chip aging (i.e., expected lifetime). Some of these effects are layout-dependent, while others occur due to manufacturing or operational variation. For example, implementing an existing analog design in new technology may expose all kinds of unexpected effects that weren’t present or significant in the previous technology. Device aging is a problem that is very hard to assess with post-layout simulation without using specific aging models. In most designs, small differences between devices are not caught by the post-layout simulation, although they can have a huge impact on the lifetime of the final product. Analog designs are also highly susceptible to variations in the manufacturing process, which can manifest as unintended consequences in the circuitry. All of these challenges can negatively impact circuit reliability and robustness in general, which can make it difficult to design circuits that perform reliably over the expected product lifetime.

While analog design schematics are usually well done and match the expected performance accurately, it is not unusual, once the physical layout of an analog design is complete and circuit implementation has been validated with layout vs. schematic (LVS) verification, for discrepancies between the schematic and physical layout to affect the quality of the final product. Many potential layout-dependent and manufacturing variation effects must be analyzed to avoid reliability and performance issues. While some of these effects can be caught during post-layout simulation, others won’t be seen until the design is on silicon, so finding and eliminating them during design verification is essential to chip success.

Layout-dependent effects
Layout-dependent effects comprise a wide range of well-known analog layout issues that have long been present and studied in established process nodes (e.g., 180nm, 130nm, 90nm). However, finding and eliminating these effects has primarily been dependent on manual reviews that rely on the designer’s experience and expertise.

There are two significant layout-dependent issues that affect analog design reliability and product lifetime:

• Well proximity effect (WPE)
• Shallow trench isolation (STI) stress

Both WPE and STI stress have a negative impact on transistor electrical parameters (e.g., threshold voltage), and thus on transistor performances [1,2]. These effects can change the circuit behavior, even if the schematic simulation is accurate.

By back-annotating the schematic with the layout parasitics, designers can perform post-layout simulations that take these effects into account, but this approach leads to design iterations that can take a long time to achieve a layout that meets the expected performance [3]. The more practical approach is to avoid creating these conditions during the initial design and layout of the circuitry.

Over the years, analog designers have developed a number of best design practices to avoid or minimize these effects. Some of these design practices include:

• symmetry between devices
• current orientation matching
• dummy device insertions
• common centroid and pitch among devices
• electrical parameters matching

Let’s look at how these design constraints can help eliminate or mitigate WPE and STI conditions.

Well proximity effect
Current mirrors and differential pairs are the most commonly used analog circuits. Figure 1 shows a current mirror with a sample layout implementation.

Figure 1: (a) Current mirror schematic, (b) one option for layout implementation of the current mirror (transistors A, B, and C).

For the devices to age symmetrically, all devices in a well must have the same spacing to the edge of the well (well proximity). Two devices with a small difference in WPE will age differently, which can lead to performance degradation and eventually a reduced product lifetime. Figure 2 illustrates a current mirror layout that does not comply with the well proximity design constraint. The outermost transistors (A1 & C) are farther from the bottom of the well than the inner two (A2 & B). While the precise quantitative effect is very process-dependent, the WPE can significantly vary the transistor speed. WPE has non-negligible effects on devices even at mature process nodes [4].

Figure 2: WPE occurs when devices are placed at greatly varying distances from the edge of the well.

To minimize WPE, all devices that are expected to behave and age similarly should be matched together, and should also have the same layout context, including spacing from the well edge. Using design constraint checks such as symmetry and device match enable the designer to ensure similar aging of different devices.

Shallow trench isolation stress
STI is created during manufacturing to enable closer spacing of transistors while preventing current leakage between them (Figure 3).

Figure 3: STI is used to isolate devices from each other (NMOS from NMOS, NMOS from PMOS, etc.)

However, the very act of creating STI also creates new stresses (Figure 4). To regulate the effect of STI stress, the shapes (polygons that define the device) of all the devices belonging to one group should be symmetrical to ensure the same stress parameters. Moreover, the shapes surrounding the devices within a certain distance (context layer) should also be the same. This uniformity ensures that not only will STI stress be the same for all the devices within the same group, but also that all the coupling will be the same (e.g., same metal1 area on top of all the devices).

Figure 4: Creating STI adds new stresses that must be accounted for and regulated.

For example, to ensure uniform STI stress behavior among the current mirror devices shown in Figure 1, they must also comply with symmetry and device match design constraints.

Manufacturing and operational variation effects
Once an analog design is taped out and sent to manufacturing, it is subject to the normal variation found in any manufacturing process. When it is placed in operation, the conditions under which it operates can greatly affect performance and product lifetime. There are two significant variation effects related to manufacturing and operation:

• Metallization process variation
• Thermal/process variation

Unfortunately, these variations cannot be anticipated, since the manufacturing process is never perfectly replicable, and most designers will have little to no insight regarding the operating environment in which the chip will be used. Minimizing the impact of these effects requires an understanding of the underlying cause, and how proper design and verification can reduce their occurrence.

One way to minimize the effect of manufacturing variation is to ensure consistency in device design. Common centroid design implements schematic devices as multiple layout devices with a common center, which helps mitigate variation effects seen by each schematic device, ensuring that different devices will vary in a similar manner during manufacturing [5].

In common centroid checking, the center of each device is determined (Figure 5). If those centers have the same location (x/y coordinates), then the devices have common centers and will experience the same average variations.

Figure 5: The centers of devices A, B, and C should be the same to ensure they all respond to manufacturing variation similarly. Here, devices C and B have a common center, but device A does not.

Figure 6 illustrates a common operating variation: environmental temperature. In this example, there are two devices, A and B. If those devices are MOS transistors, then several of their parameters, such as drain current, are linked to the environmental temperature. Consequently, devices A and B will behave differently as the environmental temperature changes. Assuming the temperature variation increases in x direction, the temperature experienced by device B will be higher than the one experienced by device A. If these devices are part of a current mirror, the output current might not match the reference current. Similarly if these devices are a differential pair, this variation will create an offset on the output of the differential pair. Such mismatches can lead to a loss of performance, especially on sensitive designs such as radio frequency (RF), analog-to-digital or digital-to-analog (AD/DA) converters, etc.

Figure 6: Devices A and B experience different average temperature/process variations, which can affect overall performance.

Figure 7 shows a possible layout design that solves the temperature variation issue. By having a common centroid between the devices, the designer can create a layout where the average variations of both devices A and B will be the same. Now, any transistor performance change due to such temperature variation will affect both transistor A and B equally, meaning they will behave similarly.

Figure 7: Layout of two source transistors (A and B) where each transistor is represented by two layout transistors. In this configuration, devices A and B will experience the same average variation.

Analog layout constraint checking
Layout constraint checking attempts to find layout-dependent and potential manufacturing variation issues before the design is taped out, to enable analog designers to eliminate or mitigate potential performance and reliability issues during the design phase.

Most analog designers are used to visually reviewing the layout with the layout engineer to find any areas in the design that do not comply with the design constraints. However, the increasing complexity and size of today’s designs means visual inspection of layout structures can be very tedious and time-consuming, especially when the design contains complex routing. Exhaustive layout reviews take time, and are always prone to human error. Additionally, after each design change, no matter how minor, the designer should ideally re-check the design. However, because of time and resource constraints, designs are often not reviewed after minor changes, which can result in small discrepancies that may not be caught by post-layout simulations.

Automated constraint checking
Fortunately, analog designers now have another option—automated constraint checking. The biggest advantage of automated constraint checking is that it is a deterministic process, meaning that the result of an automated check will always be the same for a given set of inputs, eliminating the chance of human error.

Some automated electronic design automation (EDA) constraint checking tools can automatically and accurately detect subtle errors in a variety of analog constraint checks, such as device symmetry, device orientation, the presence/absence of dummy devices, and common centroid layout accuracy. [6,7]. In an automated analog constraint verification flow, the designer determines which devices must be checked, and which check(s) should be applied to each group of devices. The constraint checking tool can then automatically check each group of devices and report any constraint violations.

Figure 8 shows a snapshot of a symmetry error highlighted using automated analog constraint checks.

Figure 8: A snapshot showing a symmetry error (around vertical axis) on a group of devices (white areas are the error geometries).

In common centroid checking, the constraint checking tools first calculates the center of each device. (Figure 9). If the centers do not match, an error is reported.

Figure 9: The constraint checking tool detected that devices A, B, and C do not have a common centroid structure (their centers of gravity are not overlapping), so they will experience different variation.

Adding dummy devices around a group (array) of devices can reduce the impact of both WPE and STI stress for the array by standardizing the distance between the active devices and the well edge, increasing the uniformity of the WPE and STI stress experienced by the active devices. The constraint checking tool can check for the presence of these dummy devices, as shown in Figure 10.

Figure 10: The Calibre PERC platform checks for the presence of dummy devices (grey) placed around an array of active devices (green) when needed to standardize spacing in an array configuration.

A key tipping point for a broad adoption of automated analog constraint checks is their inclusion in a foundry reliability process design kit (PDK). TowerJazz, a leading-edge foundry for automotive and analog products, enabled reliability-related analog constraint checks in their PDK offering, allowing TowerJazz customers to automate their analog reliability verification flows with the Calibre PERC reliability platform from Mentor, a Siemens Business [8]. A consistent evaluation process, combined with automated verification of reliability design constraints, also provides an effective method of ensuring a layout is in compliance with industry reliability standards, such as the ISO 26262 functional safety requirements for automotive IC designs, and the German-funded RESCAR 2.0 project [9], which is focused on increasing the reliability of automotive electronics (Figure 11).

Figure 11: ISO 26262 compliance, along with industry initiatives such as the German RESCAR 2.0 reliability program, are driving the adoption of automated analog constraint checking.

Conclusion
Many layout-dependent and operational environment variation effects are subtle and hard to predict. While analog designers have developed a variety of layout design best practices over the years to overcome the negative impact of variation effects, verification of these best practices has been performed predominately through visual inspection. Such visual inspection can be difficult and time-consuming, and may lead to inadvertent oversights.

Automated analog layout constraint checks can consistently identify even the most subtle discrepancies. The ability to quickly find and accurately correct these issues not only contributes to improved performance and product lifetime of the final product, but also minimizes the number of design cycles needed, which reduces overall design time and increases designer productivity. Adding automated reliability checks to the analog design and verification flow enables analog designers to consistently deliver designs on schedule, with the assurance they will perform as intended for the lifetime of the product.

References
[1] T. B. Hook, J. Brown, P. Cottrell, E. Adler, D. Hoyniak, J. Johnson and R. Mann, “Lateral ion implant straggle and mask proximity effect,” IEEE Transactions on Electron Devices, vol. 50, no. 9, pp. 1946-1951, 2003. DOI: 10.1109/TED.2003.815371

[2] J. V. Faricelli, “Layout-dependent proximity effects in deep nanoscale CMOS,” Custom Integrated Circuits Conference (CICC), 2010 IEEE, IEEE, 2010, pp. 1-8. DOI: 10.1109/CICC.2010.5617407
[3] C.-W. Lin, J.-M. Lin, Y.-C. Chiu, C.-P. Huang and S.-J. Chang, “Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits,” Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, IEEE, 2011, pp. 528-533.
[4] P. G. Drennan, M. L. Kniffin and D. R. Locascio, “Implications of Proximity Effects for Analog Design,” IEEE Custom Integrated Circuits Conference 2006, San Jose, CA, 2006, pp. 169-176. 
DOI: 10.1109/CICC.2006.320869
[5] Wu, Po-Hsun, et al., “Common-centroid FinFET placement considering the impact of gate misalignment,” Proceedings of the 2015 Symposium on International Symposium on Physical Design. ACM, 2015.
[6] Mentor, a Siemens Business. Nov. 2, 2017. “Mentor and TowerJazz provide first commercial comprehensive suite of analog constraint checks for enhanced automotive reliability offering.”
[7] V. M. zu Bexten, M. Tristl, G. Jerke, H. Marquardt and D. Medhat, “Physical verification flow for hierarchical analog IC design constraints,” in Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific, IEEE, 2015, pp. 447-453. DOI: 10.1109/ASPDAC.2015.7059047
URL: https://ieeexplore.ieee.org/document/7059047
[8] TowerJazz, 2017. “Mentor and TowerJazz provide first commercial comprehensive suite of analog constraint checks for enhanced automotive reliability offering.” November, 2017.
[9] Mentor, a Siemens Business. 2018. “Mentor’s industry-standard Calibre physical verification portfolio achieves ISO 26262 certification.” July 9, 2018.

Authors
Hossam Sarhan, Ph.D., is a Technical Marketing Engineer in the Design to Silicon division of Mentor, a Siemens Business.

Alexandre Arriordaz is a Technical Marketing Manager for Calibre Design Solutions at Mentor, a Siemens Business. He also serves as a project interface for various European projects investigating R&D topics such as 3D-IC or silicon photonics. Prior to joining Mentor, Alexandre was a full-custom design engineer, working on advanced testchip/SRAM compiler developments. He holds a Master’s degree in Electronics from the University de Nice-Sophia-Antipolis, France.