Balancing Power And Test

Tests that are power-aware and fully baked are becoming a critical part of low-power design.


The International Test Conference will be held at the Disneyland resort hotel in Anaheim, Calif., from Nov. 4-9. One of the biggest concerns for the test engineering community is to account for the impact on test quality due to additional power management techniques implemented in deep submicron designs.

Elaborate power management strategies, such as voltage scaling, clock gating or power-gating techniques are used today to control power dissipation during functional operation. The deployment of these strategies has implications on manufacturing test. Consequently, power-aware test and the need to balance both test completeness and power dissipation on the tester is becoming a major consideration during design-for-test and test preparation for low-power devices.


Designers of low power applications create “power vectors,” which are also known as “barbecue vectors” to account for the theoretical highest power-consuming functional mode of operation. These vectors are used for early power estimation at the register transfer level (RTL). Automatic test pattern generation (ATPG) tools use different techniques to generate low-power vectors. However, there is no idea of the power consumed during manufacturing test at RTL, as test vectors are only generated at the netlist level by ATPG tools. That’s too late to make design changes.

SoC designs have multiple scan chains with several thousand flops. Power dissipation is high if all the scan chains are run at the same time on the tester. Hence scan mode power is a key factor for deciding chip packaging. The power grid is designed with a certain maximum power, based on normal operational mode however.

So, finding scan power early in the design phase, i.e., at RTL is very important. If the estimated power is not under budget, then one needs to explore options to reduce power.

Here are a couple of options:

  1. Run the tests at lower speed on the test equipment.
  2. Divide and conquer the SoC and run tests on only select groups of blocks.

Another issue with power during test is the IR drop caused by simultaneous switching of capture clocks during at-speed testing. This can be avoided by selecting a group of capture clocks for only certain blocks in the design.

SoCs are designed with groups of scan chains. If we can run one scan group at a time on the tester, then we can reduce the power with an increase in the test time. So, we need to find the minimum number and arrangement of scan groups which will avoid the power limit. Atrenta’s SpyGlass Power can be used to estimate the test mode power early at RTL for different configurations of the scan groups to help with the power grid design.


Using these design-for-test techniques can cause excess cost due to higher test time on the tester. Is all this worth it? Designers working on low power applications think so as they are implementing these solutions today to achieve the proper balance for testability and power, for both functional and manufacturing test modes.